kuntul
Newbie level 6
I am implementing a single cycle datapath in verilog and it has an ALU inside of it. One of the ALU functionality is to add.. and I did use the verilog '+' sign for this. If I had another module to perform add using gate level, will this make my clock speed much faster when I synthesize?
The report that I got when synthesizing is around 25Mhz and I want it to be around 40 MHz
The report that I got when synthesizing is around 25Mhz and I want it to be around 40 MHz