Asynchronous FIFO vs Multi cycle path (MCP) clock domain crossing

[abhinavpr]

Hi,
Can anybody tell me the advantages of using Asynchronous FIFO when we can do the clock domain crossing using multicycle path cdc (synchronizing control enable signal and holding the input data for mulitple cycles ). why go for the pains of creating a fifo and verifying it also adding significant gate count to the design.


-abhinavpr

 

[NEOSCHIP TECHNOLOGIES]

In this case you need to make the source logic to wait and check till it gets synced into destination logic, if you are transferring data in bursts then its lot off overhead on Bandwidth requirements. Fifo does in burst and having an extra buffer depth will continue with write burst. Thus very limited back pressure.