Assigning submatrix to matrix in VHDL

[sim1234]

Hi,

I've got the following problem: I've defined a matrix type as

type matrix is array (natural range <>, natural range <>) of pixel;

where pixel is a SLV with a given length.

Now I have an entity that takes such a matrix as input (e.g. (2 downto 0, 19 downto 0). Within that entity I want to split that matrix into several submatrices with the same height (2 downto 0) but different width depending on in how many parts it should be split (e.g. 19 downto 10 and 9 downto 0). These submatrices are then the input of several subentities within the top entity. The input ports of these subentities are also of type matrix but with the appropriate size. I then tried to assign the corresponding submatrices by

SubEntIn <= EntIn(2 downto 0, XXX downto YYY);

where XXX and YYY are expressions depending on some index i. This however gives the following error

Only one discrete range allowed in slice name of "entin".
Cannot resolve indexed name as type sub-array #1 of work.somepackage.matrix.

What am I doing wrong? And what solution would you suggest?

Thanks.

 

[TrickyDicky]

2d arrays are a bit more complicated than 1d arrays. Basically you cannot do what you are doing. Its because it doesnt know that the slicing you have done is actually the correct type.

Id write a function that pulls the elements out one by one inside a for loop. That will work.