Assigning more than one task to a state (in WITH statement)

[Opel_Corsa]

In the following sample code a state machine is defined:

architecture RTL of mycode is
	type state_type is (I0,I1,I2,I3,I4,I5,I6);
	signal y : state_type;
	signal var_x, var_y : std_logic;
begin
	process(clk, reset)
	begin
		if (reset = '1') then
			var_x <= '0';
			y <= I0;
		elsif (clk'event and clk = '1') then
				case y is
					when I1 => y <= I2;
					when I2 => y <= I3;
					when I3 => y <= I4;
					when I4 => y <= I5;
					when I5 => y <= I6;
					when others => var_x <= '0';
								y <= I1;
				end case;
		end if;
		end process;

		with y select
			outputscr <= "00000000" when I0,
						"00111000" when I1,
						"00111000" when I2,
						"00001100" when I3,
						"00000001" when I4,
						"00000110" when I5,
						"10000000" when I6;

end RTL;

As you see, there's one task given to each state (at the last part of the code, the with-select section). e.g. outputscr is assigned 0 when in state I0. Now, what I want to do is to define more tasks for, say, I0. For example, when in state I0, I want to assert 0 on outputscr, set var_x, and unset var_y. I'm wondering what is the syntax for doing this.

Any help is appreciated.

 

[nand_gates]

Re: Assigning more than one task to a state (in WITH stateme

Its very simple..

architecture RTL of mycode is
   type state_type is (I0,I1,I2,I3,I4,I5,I6);
   signal y : state_type;
   signal var_x, var_y : std_logic;
begin
   process(clk, reset)
   begin
      if (reset = '1') then
         var_x <= '0';
         var_y <= '0';
         y <= I0;
      elsif (clk'event and clk = '1') then
            case y is
               when I1 => y <= I2;
               when I2 => y <= I3;
               when I3 => y <= I4;
               when I4 => y <= I5;
               when I5 => y <= I6;
               when others =>       -- I0 is default state
                        var_x <= '1';  -- set var_x
                        var_y <= '0';  -- reset var_y
                        y <= I1;
            end case;
      end if;
      end process;

      with y select
         outputscr <= "00000000" when I0,
                  "00111000" when I1,
                  "00111000" when I2,
                  "00001100" when I3,
                  "00000001" when I4,
                  "00000110" when I5,
                  "10000000" when I6;

end RTL;

 

[Opel_Corsa]

Re: Assigning more than one task to a state (in WITH stateme

Thanks for your reply, but that was not what I was looking for. I was wondering if it is possible to do something like the following:

with y select
         {outputscr <= "00000000", var_x <= '1', var_y <= '0'} when I0,
                  "00111000" when I1,
                  "00111000" when I2,
                  "00001100" when I3,
                  "00000001" when I4,
                  "00000110" when I5,
                  "10000000" when I6;

Yes, I know that's not the correct syntax, and that's exactly my question; how do I assign more than one task (or whatever you may call it) to each state? I'm wondering if it is possible to implement this in the WITH-SELECT part, and not within the process.

 

[nand_gates]

Re: Assigning more than one task to a state (in WITH stateme

This is one more way to do it but this will create latch for var_x and var_y!

architecture flow of unknown 
    signal outputscr_x_y : std_logic_vector(9 downto 0);
begin
with y select
     outputscr_x_y <= "00000000" & '1' &'0' when I0,
                      "00111000" & var_x & var_y when I1,
                      "00111000" & var_x & var_y when I2,
                      "00001100" & var_x & var_y when I3,
                      "00000001" & var_x & var_y when I4,
                      "00000110" & var_x & var_y when I5,
                      "10000000" & var_x & var_y when I6;

outputscr <= outputscr_x_y(9 downto 2);
var_x     <= outputscr_x_y(1);
var_y     <= outputscr_x_y(0);

 

[xstal]

Re: Assigning more than one task to a state (in WITH stateme

Hi,

you can assign value to only one signal using "with...select" statement. As you want to trigger more than one signal in one state, you will have to use separate "with...select" statements for each signal. These signals will get updated concurrently and hence you can perform more than one task in one state using "with....select" statement.

Good Luck!!!!!

 

[Opel_Corsa]

Re: Assigning more than one task to a state (in WITH stateme

Thanks! That's very smart, nand_gates. So now I realize that it's not possible to do what I was looking for (as xstal mentioned) other than by tweaking the design by a bit.

 

[Elephantus]

Re: Assigning more than one task to a state (in WITH stateme

Hi. As per discussion in the other thread(If- Then VHDL error), there is an alternative way of doing this.

architecture RTL of mycode is
   type state_type is (I0,I1,I2,I3,I4,I5,I6);
   signal curr_state,next_state : state_type;
   signal var_x, var_y : std_logic;
begin
   -- state machine synchronous process
   process(clk, reset)
   begin
      if (reset = '1') then
         curr_state <= I0;
      elsif (clk'event and clk = '1') then
      	 curr_state <= next_state;
      end if;
   end process;

   -- state machine combinatorial process
   process(curr_state) is
   begin
    -- default output values
    var_x <= '0';
    var_y <= '1';
    outputscr <= "00000000";
    -- decoding of state and outputs
   	case curr_state is
   	  when I0 =>
   	  	next_state <= I1; -- decode next state
   	  	var_x <= '1'; -- assign outputs
   	  	var_y <= '0';
          when I1 => 
      		next_state <= I2;
      		outputscr <= "00111000";
          when I2 => 
                 next_state <= I3;
                 outputscr <= "00111000";
          when I3 => 
                 next_state <= I4;
                 outputscr <= "00001100";
          when I4 =>
                 next_state <= I5;
                 outputscr <= "00000001";
          when I5 =>
                 next_state <= I5;
                 outputscr <= "00000110";
          when I6 => 
                 next_state <= I6;
                 outputscr <= "10000000";
      -- default transition      
          when others => 
      		 next_state <= I0;
	end case;        
   end process;
     
end RTL;