ASIC implementation of segmentation algorithm

[subujohn]

Is it possible to develop HDL Verilog code for segmentation algorithm from scratch?

 

[mrflibble]

Is this a loaded question? Or more like a rhetorical question? Does HDL Verilog code for segmentation algorithm exist? If yes, then yes.

 

[jeffrey samuel]

Why is this any form of Hw what is the point any way I find this is a Project you have in hand

 

[subujohn]

@JEFFREY SAMUEL: This is part of my project...I was told to extend my project into ASIC domain once I'm done with the FPGA implementation of the segmentation algorithm, where I'll be using the code generated from system generator.

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Is this a loaded question? Or more like a rhetorical question? Does HDL Verilog code for segmentation algorithm exist? If yes, then yes.

Just wanted to know if it can be done...My plan was to develop HDL verilog code, make it synthesizable and then dump onto a FPGA....After which I'll send an image across to FPGA and do the image segmentation.