bejoy
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ARM9 int handler
Code:
.global entrypoint
.sect ".handlers"
.global Reset_Handler,Undefined_Handler,SWI_Handler,Prefetch_Handler
.global Abort_Handler,IRQ_Handler,FIQ_Handler
entrypoint:
Reset_Handler:
B Reset_Handler1
Undefined_Handler:
B Undefined_Handler
SWI_Handler:
B SWI_Handler
Prefetch_Handler:
B Prefetch_Handler
Abort_Handler:
B Abort_Handler
NOP
IRQ_Handler:
B IRQ_Handler
FIQ_Handler:
B FIQ_Handler
Mode_USR .set 0x10
Mode_FIQ .set 0x11
Mode_IRQ .set 0x12
Mode_SVC .set 0x13
Mode_ABT .set 0x17
Mode_UND .set 0x1B
Mode_SYS .set 0x1F ; available on ARM Arch 4 and later
I_Bit .set 0x80 /? ;when I bit is set, IRQ is disabled
F_Bit .set 0x40 /? ;when F bit is set, FIQ is disabled
Len_FIQ_Stack .set 512
Len_IRQ_Stack .set 512
Len_ABT_Stack .set 512
Len_UND_Stack .set 256
Len_SVC_Stack .set 1024
Len_USR_Stack .set 1024
Offset_FIQ_Stack .set 0
Offset_IRQ_Stack .set Offset_FIQ_Stack + Len_FIQ_Stack
Offset_ABT_Stack .set Offset_IRQ_Stack + Len_IRQ_Stack
Offset_UND_Stack .set Offset_ABT_Stack + Len_ABT_Stack
Offset_SVC_Stack .set Offset_UND_Stack + Len_UND_Stack
Offset_USR_Stack .set Offset_SVC_Stack + Len_SVC_Stack
Reset_Handler1:
LDR r0, stack_s //r1
MSR CPSR_c, #Mode_FIQ | I_Bit | F_Bit ; No interrupts
SUB sp, r0, #Offset_FIQ_Stack
MSR CPSR_c, #Mode_IRQ | I_Bit | F_Bit ; No interrupts
SUB sp, r0, #Offset_IRQ_Stack
MSR CPSR_c, #Mode_ABT | I_Bit | F_Bit ; No interrupts
SUB sp, r0, #Offset_ABT_Stack
MSR CPSR_c, #Mode_UND | I_Bit | F_Bit ; No interrupts
SUB sp, r0, #Offset_UND_Stack
MSR CPSR_c, #Mode_SVC | F_Bit ; No interrupts I_Bit |
SUB sp, r0, #Offset_SVC_Stack
LDR R0,op1_s
LDR R1,[R0]
loop: B loop
stack_s .word top_of_stack
op1_s .word op1
.sect ".stack"
top_of_stack:
.sect ".math_memory"
op1 .word 0x12345678
op2 .word 0x23456789
res .word 0x00000000[color=red][/color]