anybody offer me some material about vco design?

[ithink]

i must design vco operating under 100MHz, but i never do it ,so i hope anybody offer some circuit to me.
thanks!

 

[massive]

Check the paper that is attached. It describes frequency synthesizer and you can see how the vco is designed.

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TITLE: A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V/5 V operation

ISSUE: IEEE Journal of Solid-State Circuits, vol. 32, pp. 582 - 586, April 1997

AUTHORS: Howard C. Yang, Lance K. Lee, and Ramon S. Co

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ABSTRACT:

This paper describes a phase-locked loop (PLL)- based frequency synthesizer. The voltage-controlled oscillator (VCO) utilizing a ring of single-ended current-steering amplifiers (CSA) provides low noise, wide operating frequencies, and opera- tion over a wide range of power supply voltage. A programmable charge pump circuit automatically configures the loop gain and optimizes it over the whole frequency range. The measured PLL frequency ranges are 0.3-165 MHz and 0.3-100 MHz at 5 V and 3 V supplies, respectively (the VCO frequency is twice PLL output). The peak-to-peak jitter is 81 ps (13 ps rms) at 100 MHz. The chip is fabricated with a standard 0.8-µm n-well CMOS process.
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Good luck!