AND gate clock gatinig check

[littlefield]

In my design, I use an AND gate worked as a clock gating cell, this is the RTL simulation result of this circuit.

__A________________ B _______ C_______ D _____ time

__|￣￣|____|￣￣|____|￣￣|____|￣￣|____|￣￣ clk1

__|￣￣￣￣￣￣￣￣￣￣￣￣￣￣￣￣|____________ enable

__|￣￣￣￣￣￣￣￣￣￣ | ________________ |￣￣ clk2

__|￣￣￣￣￣￣￣￣￣￣ | _____________________ output

‘enable’ is the clock gating control signal; it is in clk1 clock domain.
‘clk2’ is the clock to be gated.
‘output’ is the output of AND gate.

By default,
PT checks setup time from C (enable) to D (clk2).
PT checks hold time from A (enable) to B (clk2).
But in my opinion,
PT should check setup time from A (enable) to A (clk2),
check hold time from C (enable) to B (clk2).
Is it right?
I constrain the setup timing check:
set_multicycle_path 0 -to enable -setup -start
How to constrain the hold time check?

 

[yx.yang]

To be honest, this isn't a good design.
Using ASYNC (cross clock domian) signal to do clock gating enable is dangerous, even using latch based clcok gating is dangerous. Even DC(Design Compiler) will not insert AND gate based clock gating at ASYNC point.
Keep this in mind: why people need do special SYNC logic a cross clock domian point? Then we can get the idea whether this is safe or not. Just thinking the basic principle

 

[lostinxlation]

In my design, I use an AND gate worked as a clock gating cell, this is the RTL simulation result of this circuit.

By default,
PT checks setup time from C (enable) to D (clk2).
PT checks hold time from A (enable) to B (clk2).
But in my opinion,
PT should check setup time from A (enable) to A (clk2),
check hold time from C (enable) to B (clk2).

Setup check should be done from C to D and I think PT is correct.
For hold, I guess it should check from D to D.

But the assumption is the clock gating is done by a typical low through latch and clk1 and clk2 are synchronized, where clk1 and clk2 come from the same clock source.

 

[littlefield]

To be honest, this isn't a good design.
Using ASYNC (cross clock domian) signal to do clock gating enable is dangerous, even using latch based clcok gating is dangerous. Even DC(Design Compiler) will not insert AND gate based clock gating at ASYNC point.
Keep this in mind: why people need do special SYNC logic a cross clock domian point? Then we can get the idea whether this is safe or not. Just thinking the basic principle

clk2 is generated from clk1, so they are not ASYNC.

---------- Post added at 02:04 ---------- Previous post was at 01:57 ----------

Setup check should be done from C to D and I think PT is correct.
For hold, I guess it should check from D to D.

But the assumption is the clock gating is done by a typical low through latch and clk1 and clk2 are synchronized, where clk1 and clk2 come from the same clock source.

if the gating cell is ICG or latch based clock gating cell, what you said is correct;
however, i use the ADN gate, so it should check from A to A for setup.

 

[lostinxlation]

ok, then you can use a negative multicycle path for hold.

 

[yx.yang]

clk2 is generated from clk1, so they are not ASYNC.

---------- Post added at 02:04 ---------- Previous post was at 01:57 ----------

Hi, littlefield:
Even clk2 is generated from clk1, when you need consider the OCV effiect in 0.13us, 90ns, this is not easy to meet timing after place and route. This is becasue the two have totally different clock tree, then cauing a lot delay difference, then cauing timing analysis under OCV mode fail.