[SOLVED] Analog to Digital Converter

[amit.31]

Hi

I have to work on CMOS implementation of ADC. The specifications to my ADC are:
sampling rate:40ksps
resolution: 12 bits.

With these specification i can work with Σ-Δ ADC or successive approximation ADC.

Now firstly i want help in deciding like with which type of ADC from above two i should prefer n why?
And secondly i want to ask if other type is available or not other then these two.

Any help would be greatly appreciated....:smile:

 

[barry]

1) Generally you can get Successive-approximation type to run at higher sample rates than Sigma-delta; for your requirements not an issue
2) Other types: Flash; Dual-slope(very slow signals only, but simple implementation); Voltage-to-frequency converter

 

[JoannesPaulus]

Not knowing what the other specifications are, I believe you should consider the ΔΣ-ADC architecture since your sampling rate is low enough to give you a very high oversampling rate. I also believe that the SAR architecture is a good solution but it would require a slightly more challenging design effort. I also vote against the flash ADC (too many comparators), the dual-slope ADC (163MHz clock rate!).

 

[amit.31]

Well tnks a lot

Not knowing what the other specifications are, I believe you should consider the ΔΣ-ADC architecture since your sampling rate is low enough to give you a very high oversampling rate. I also believe that the SAR architecture is a good solution but it would require a slightly more challenging design effort. .

Would u plz help me to tell u like "what other specfications could be?"
n also what actually do u mean from "SAR requires more challenging design effort than delta sima adc"

with regards:smile:

 

[JoannesPaulus]

Other specifications that will help you decide on the right architecture for your design are, for instance power, consumption and area. The delta-sigma ADC and the SAR ADC could use one comparator. The DS will require a decimation filter while the SAR will require some sequencing logic. I believe they are fairly comparable for the given task but the devil is in the details...

 

[amit.31]

Hi sir,

After studying and analysing a lot about theses two ADCs ,i have chosen DS ADC to start work with due to its innate advantages over SAR ADC for my requirements(low sampling rate(40ksps) & medium resolution(12 bits)).
Now i m heading towards the architecture like i believe that higher order SD ADC would be a better option than 1st order SD ADC due to better noise shaping as compared to the later one.
But dont you think that higher order DS will lead to unstability of the system due to phase turn of cascaded integrators.

So I want your advice actually like should i go for higher order architecture or firstly try for first order DS ADC.

Any help would be greatly appreciated and thanks in advance.

 

[JoannesPaulus]

I believe you made the right choice and I do not think instability will be a big issue (even though you still need to take care of it). A first order DS will not achieve the required SNR unless you have huge oversampling. I would consider a third order modulator with an OS of 32.