Analog IC Design Prospective

[mbright]

Seems to me that quite a few ppl on this board r doing analog IC design or relative stuff.

Let us share and discuss some idea and prospective in the area.

1. Shrinking feature size.
Digital has come to 90nm, while analog doesn’t scale that fast and has a gap in process technology with digital.

My view: analog feature may require a certain transistor size, which mean u can not keep scaling down the device while only maintain the W/L ratio.
A simple example is that the flicker noise of a MOS transitory is inversely proportional to W*L, so most Opamp have a pretty large PMOS input pair. (of course u wanna a decent gain as well)

2 Low power
Not like digital, power consumption due to biasing DC current is the dominative portion for analog circuits.

My view: As switching factor is no longer a metric u can play tricks, low power analog design means low-supply-voltage in most cases. Clock gating/sleep mode is useless coz biasing is always there no mater u have clock or not. And low Vth is desired, leakage current is not a big deal, unless for those transistors used as switches.

Ultra-low-power circuits which operate in sub-threshold region can only provide limited speed. (most r current mode)


3. Adaptive architecture
Parameters change dynamically according to the characteristics of incoming signal, is highly desirable in many applications.

My view: Programmable device give digital great adaptive/reconfigure ability, while trade-off for hardware redundancy. Adaptive architectures are not widely used in analog circuits
FPAA seems not to be a trend, maybe just because analog circuits, by nature, are application-specific, or it can’t afford the overhead.


4. Integrated ability
Highly depends on process.

My view: Voltage mode circuits generally require large capacitors, thus double-poly process. RF/Power circuits may need ultra-large capacitors and inductors, off-chip become the only option in that case.
Current-mode circuits have many limitations on performance.

Real integration of mixed-signal system-on-a-chip may not be economically wise.

Those products (so called “mixed-signal SoC”) from industry are actually system-in-package, i.e. many small dies in one package.


5. Die or not.

Not until human being can digitalize themselves.


Any comments or correction or proposals r welcome
Sorry for my bad expression.


:roll:

 

[sunking]

An other is RF

 

[visualart]

Seems to me that quite a few ppl on this board r doing analog IC design or relative stuff.

Let us share and discuss some idea and prospective in the area.

1. Shrinking feature size.
Digital has come to 90nm, while analog doesn’t scale that fast and has a gap in process technology with digital.

My view: analog feature may require a certain transistor size, which mean u can not keep scaling down the device while only maintain the W/L ratio.
A simple example is that the flicker noise of a MOS transitory is inversely proportional to W*L, so most Opamp have a pretty large PMOS input pair. (of course u wanna a decent gain as well)

2 Low power
Not like digital, power consumption due to biasing DC current is the dominative portion for analog circuits.

My view: As switching factor is no longer a metric u can play tricks, low power analog design means low-supply-voltage in most cases. Clock gating/sleep mode is useless coz biasing is always there no mater u have clock or not. And low Vth is desired, leakage current is not a big deal, unless for those transistors used as switches.

Ultra-low-power circuits which operate in sub-threshold region can only provide limited speed. (most r current mode)


3. Adaptive architecture
Parameters change dynamically according to the characteristics of incoming signal, is highly desirable in many applications.

My view: Programmable device give digital great adaptive/reconfigure ability, while trade-off for hardware redundancy. Adaptive architectures are not widely used in analog circuits
FPAA seems not to be a trend, maybe just because analog circuits, by nature, are application-specific, or it can’t afford the overhead.


4. Integrated ability
Highly depends on process.

My view: Voltage mode circuits generally require large capacitors, thus double-poly process. RF/Power circuits may need ultra-large capacitors and inductors, off-chip become the only option in that case.
Current-mode circuits have many limitations on performance.

Real integration of mixed-signal system-on-a-chip may not be economically wise.

Those products (so called “mixed-signal SoC”) from industry are actually system-in-package, i.e. many small dies in one package.


5. Die or not.

Not until human being can digitalize themselves.


Any comments or correction or proposals r welcome
Sorry for my bad expression.


:roll:

Terrific!

U a right!
But the Power IC, wave Power IC, High voltage IC, etc is the relate to the analog.

 

[selvaraja]

Hai ,

analog never die field...................

 

[cetc1525]

analog ic will not die because our real world is variety,it need something change to the digital world.
the future is the mixed ic.

 

[Puppet1]

Now we are getting into nanotechnology and more physics based design.

An Analog Circuit will always be needed for data conversion and fast signal processing.

 

[emilian6]

Of course,
Nature is Analog,
Digital is Artificial.
Mix them is our world.
If one is missing, the world is missing

 

[mbright]

OK, ppl on this board all agree with :?: analog “never die”.

Now let’s discuss some tech. issues.

The question is that will analog IC shrink as digital counterpart?
Can device still maintain decent analog feature in nanometer scale?

In analog, most transistors r used as amplifying device, not as switches in digital, so with sufficient gain and reasonable noise ratio, u can’t make it too small, hence the benefits of new process r not as much as digital.

(In one word, the die area doesn’t scale as feature size)

So why bother 90nm analog design?
:?:

 

[Puppet1]

abidi has a recent paper on RF CMOS and CMOS in general for analog design.

he thinks its done now, but for further nanometer design, you need signal processing, calibration and trimming for analog circuits, dual threshold design.

you will see more system level IC designs, and more algorithms and circuit tricks, and multi threshold.

 

[cetc1525]

analog can work at high voltage.

 

[crystal]

Performance of analog design is being looked more seriously at current-mode now.
There's a point where analog design can't be improved based on voltage-mode as there's a limit to it. That's part of the reason people are looking at current-mode.

 

[leo_o2]

Though analog circuit will not die, I think most analog guys should die. Now more and more guys come to this field but job opportunity is few. In additional, market also asks for larger chip that include more and more functions. But nearly all designs will be completed by hand. Any error will crash it.

 

[mbright]

For multi-thresholds:

It is basically a power issue. As I said power consumption in analog IC is mainly due to DC biasing current, means no tricks on switching factor. Multi-threshold is desirable since when u scaling VDD, u can still have decent signal swing by scaling Vth, besides the leakage benefit.

But multi-thresholds design leaves the headache to fab .guys. In order to have multiple Vth values, u need either bulk biasing (means more separate wells and pins), or floating-gates (means high voltage Vth programming).

So dual-threshold may be affordable. Any real multi-threshold process?



For current mode circuits:

What I heard is an inverse.
I did my M.S. on switched-current circuits, but there r many limitations on the performance, especially the noise due to CFT/CI.
This is obvious. In SC circuits, charge r stored in large linear capacitors, u can expect a good SNR.
While in SI circuits charge r stored in intrinsic capacitance of transistors (very small), even a small amount of charge coupling through the CK will deviate ur signal.

Ultra-low-power current mode circuits operate in sub-threshold region, relationship of voltage and current is exp. not sqr.
It seems to me just like using CMOS as BJT, u do have a large input resis. though.
But the speed of this kind is awful.


Or we came back to, no-switch, pure continues, current mode processing?


As to job, yes, many Chinese and Indian students come to the field. But still less than DSP, commu. and digital.
Make analog design a 2nd CS case?
Not really I believe.

 

[thisnot]

is rf design the most popular field right now in the industry? (in respect to analog ic)

 

[Colbhaidh]

As an old man still in wafer fabrication, it is amaazing to see how analogue design is positively flourishing as chip technologies scale even lower. It is probably true to say that as the industry scaled to 0.18um 0.13um 0.1um and 90nm, the analogue part of the chip scaled 0.35um 0.30um, 0.30um and still considering ....
However there are very interesting work arounds in silicon just now.
For noise, I have seen several designs where noise cancellation techniques are used (feeding inverse noise into critical circuits).
Where layout induced offsets in matched components are immpossible to avoid with advanced scaled cmos, techniques for sampling offsets then cancelling the residual are common.

Another thing worth considering - if you cant go down, go up ...
There is a huge untapped market for high voltage + high current applications. The market does not really exist because there is no good solution yet. But it is only a matter of a few years.

I do not think the extinction of the analogue designer species is any time soon, but then again, there may be an asteroid around the corner.

 

[Puppet1]

do you think analog design with go to indium phosphide or sige bipolars instead of cmos ?
90nm CMOS cannot do most high frequency applications (40ghz and above)

 

[mbright]

Colbhaidh's post is really informative. i appreciate that.

my question:

AS to so called "advanced nosie cancellation techniques", seems to me most of them r just duplicate ur circuits more and more and then applied a inverse CK(or any noise source), is the overhead a little bit high?

could u give me a brief idea about how to sampling offsets?


i'm working on low-powe, so maybe naive to high woltage.
where and why do we need high voltage? except power amplify?
we always demand low power, right? coz we don't want to re-charge the battary to frq. besides, anybody like to attach a big fan on ur cute chips?

 

[Colbhaidh]

On the contrary, high voltage is becoming very important in the field of energy conservation. In a few years time, you will not be able to buy a light bulb without some IC on board. Also, automotive is a huge market and quite lucrative. eventually governments will probably dictate that you must use smart power so its an interesting field to explore.

On the topic of offset reduction, just short the inputs to the Amp and sample the output by a capacitor (Sample & Hold) the subtract that from on of the inputs. It does require some overhead and not every design can allow this kind of technique.

 

[jebi]

I thnik the new applicaitons will still come in the future.

 

[qutang]

i think analog will have a new way now in the advanced companies.