JohnG300c
Advanced Member level 4
I'm attempting to use the Autorouter in Altium Designer to simplify with the fan-out and escape routing of my 780-pin FPGA (8-layer PCB). I have found that the fan-out vias placed by the Situs autorouter are all full-stack vias although both blind and buried vias are defined too (via layer-pairs in the Layer Stack Manager). Use of full-stack vias cause the routing of most nets to fail due to lack of space between the full-stack vias on all layers.
Is there any way to make the AD autorouter actually properly fan out and escape route using an optimal combination of blind and buried vias? It seems completely broken...
I have started playing around with manually changing vias to blind vias but it is a huge job which essentially negates the availability of the autorouter!
Thanks in advance.
Is there any way to make the AD autorouter actually properly fan out and escape route using an optimal combination of blind and buried vias? It seems completely broken...
I have started playing around with manually changing vias to blind vias but it is a huge job which essentially negates the availability of the autorouter!
Thanks in advance.