therealpaulie
Newbie level 6
Hi,
(1) Can I use alias for type? I would like something like:
I don't want to write for all my signals "std_logic(0 downto 12)". It's easier if I use an alias like:
(2) How do I access a column from a std_logic_vector2(0 to 2, 15 downto 0). The Xilinx ISE generates such a signal for Post-Route simulation and I cannot handle it right in the test bench.
I want for example
Paul
(1) Can I use alias for type? I would like something like:
alias my_type : std_logic(0 downto 12);
I don't want to write for all my signals "std_logic(0 downto 12)". It's easier if I use an alias like:
signal one : my_type;
(2) How do I access a column from a std_logic_vector2(0 to 2, 15 downto 0). The Xilinx ISE generates such a signal for Post-Route simulation and I cannot handle it right in the test bench.
I want for example
Code:
signal one : std_logic_vector2(0 to 2, 15 downto 0);
one(0)(everything) <= x"AA";
Paul