Alias for a type and std_logic_vector2

[therealpaulie]

Hi,

(1) Can I use alias for type? I would like something like:

alias my_type : std_logic(0 downto 12);​

I don't want to write for all my signals "std_logic(0 downto 12)". It's easier if I use an alias like:

signal one : my_type;​

(2) How do I access a column from a std_logic_vector2(0 to 2, 15 downto 0). The Xilinx ISE generates such a signal for Post-Route simulation and I cannot handle it right in the test bench.
I want for example

signal one : std_logic_vector2(0 to 2, 15 downto 0);
one(0)(everything) <= x"AA";

Paul

 

[TrickyDicky]

many problems here:
1. std_logic is not an array type. std_logic_vector is
2. You cannot use (0 downto 12). This is a null array. You mean (12 downto 0) or (0 to 12)
3. use a subtype to create your own type.

subtype my_type is std_logic_vector(12 downto 0);

signal one : my_type;

4. you cannot have a 2D std_logic_vector like that. you have to declare an array type of std_logic_vector (or my_type)

type std_logic_vector2 is array(0 to 2) of my_type;

signal one : std_logic_vector2;

 

[therealpaulie]

hi trickydicky,

1-3. I wrote everything in a hurry and very late in the night. Yes I wanted to write: std_logic_vector(12 downto 0). Sorry for posting with a lot of mistakes. Yes, it's so simple with subtype, thanks.

4. There is a standard std_logic_vector2 type. You can find it in the SIMPRIM library. In xilinx ISE if you generate the files for the POST-ROUTE simulation you will get a "my-file"_timesim.vhd file. All the components for POST-ROUTE simulation can be found in SIMPRIM library. And in this library the std_logic_vector2 type is defined.

These are some lines from an automatically generated Xilinx ISE file:

-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity my_entity is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    output1 : out STD_LOGIC_VECTOR2 ( 2 downto 0 , 15 downto 0 ); 
    output2 : out STD_LOGIC_VECTOR2 ( 2 downto 0 , 15 downto 0 ); 
    input1 : in STD_LOGIC_VECTOR2 ( 2 downto 0 , 15 downto 0 );

Paul

 

[TrickyDicky]

the SIMPRIM library is not standard, it is a XILINX library. And the big big problem with 2d vectors of std_logic is that they are not compatible with std_logic_vector, so you have to use functions to assign std_logic_vectors to std_logic_vector2. (or loops)

Personally I would avoid std_logic_vector2. It is a kludge that is not very user freindly.

 

[FvM]

It's easy to add std_logic_vector2 to your code without using the said library:

TYPE std_logic_vector2 IS ARRAY ( NATURAL RANGE <>,NATURAL RANGE <>) OF std_logic;

But you have to consider how you want to assign it's slices to std_logic_vector and vise versa. I assume, that the Xilinx library has functions for it, otherwise you have to define it yourself.

 

[permute]

it looks like, at least for sim, the syntax should be something along the lines of x(1,x'range(2)). No idea if that actually works, or what type it returns. I suspect it is an error, but might be useful to make a function "get_col(slv2,int) return slv". it looks like 'left, 'right, 'high, 'low, 'length, and 'range all support an argument for the dimension.

 

[FvM]

At least my tool (Altera Quartus) gives an error that slices aren't allowed for multi-dimensional objects. I'm under the impression, that it's a general VHDL restriction, but I didn't check with the IEEE standard.

 

[TrickyDicky]

You cannot slice a multi dimensional array, you have to either assign the whole lot, or 1 entry at a time, so a function is needed if you want to assign whole buses.

as for attributes, you have to specify the dimension of the attribute, like 'range, 'left etc.

 

[permute]

possibly more helpful to the OP:
many vendors prefer arrays of arrays. eg:
type my_array is array (natural range <>) of std_logic_vector(x downto y);

this fits very well into the concepts of RAMs/ROMs, as wells a arrays. It isn't a good model for matricies though -- as you've noticed there is no simple "get column" construct. (or transpose, ect...)

Because Xilinx/Altera both seem to prefer this array-of-array construct, I suggest you think about using it as much as possible. Even when the vendor's tools do allow 2-d arrays, it is more likely that they will do a better job with the aoa syntax than with some syntax that they make no claims to.

 

[FvM]

many vendors prefer arrays of arrays.

Yes, and most VHDL programmers, too. I never used the said two-dimensional array construct before.

But if I understood the original post correctly, the 2D-array is used by a Xilinx tool, so it's necessary to manage a conversion. A solution has been already suggested in the previous posts.