adressing with hyper terminal

[sarah23]

im using hyper terminal to send addres to a rom so that particular output it shows ...i have done everything ...my coding is in verilog ...it shows perfect results with a simulator but with a hyper terminal its does not ....plx suggest me something ...im attaching my code with it

 

[vsheladiya]

Hi Sarah,

I have seen your verilog code but i didn't get exactly what you want to do. which type of hardware are you using? describe the problem in brief.

 

[sarah23]

i am using spartan3 board...i send a character 'l' through hyper terminal ...uart_rx with fifo receives it on fpga and send that input data to this rom ...as a result the output 32 bit data does through fifo_tx to uart_tx and result should be shown on hyper terminal ..but it does not... now problem which i think is with this fifo buffer registers because fifo_rx it takes 8 bit input data (from uart_rx) and output 32bit data and vice-versa with fifo_tx and i can't figure out how to include such concatenation logic inside fifo that it will change data 4rm 8 -->32 & 32-->8 ......may be u can help me i am attaching my fifo code with it ...plz take a look at it

 

[vsheladiya]

Hi Sarah,
As I have worked with uart in microcontroller, for communicating uart with hyterterminal of a PC the baud rate and other control information should be set properly otherwise it will not setup a link between pc and a device. Also in hyper terminal.txt there is no clock used, are you sending the data with pc compatible baud rate?
And for fifo, if you have doubt on fifo then why are you not using Xilinx core generator FIFO?

 

[sarah23]

buad rate is exactly f9 i hav configured it properly...u mentioned abt the clock in the hyperterminal.txt is this necessary ..?ok i will change it ...the fifo available in core generator do the same thing as my fifo does , imean they will input same amount of bits buffer them and same will be the output but my requirement is 8 bit at input but 32 bit at output ....any suggestions or code available ?

 

[vsheladiya]

Baudrate f9 means? It is 249 in decimal but there is no such kind of baud rate available in hyperterminal. It should be compatible with one of the baud rate of a hyper terminal and you need to send data on that much of baud rate speed. Just confirm it.
I was suggesting Xilinx fifo because it is guaranteed to work if there is any issue in your fifo. But I was not sure whether it supports different read/write port width or not.
For reference you can visit opencores.org. The uart IP core is available on it if you find any help from it.

 

[sarah23]

i am using 19200 buad-rate and have checked its output on hyper-termial ...its working ok u can take a look on my top-level module but when i intertace my hyper_terminal.txt code b/w two FIFOS it does't work ...!

 

[vsheladiya]

if you have doubt with fifo design then you can test your design by just bypassing the fifos. I mean you can connect tx and rx using register and try to send/receive one word of data. as i understood in this case you need not to convert data from 8<->32, am i right?