ADC Measurement problem [Need expert opinion]

[wandola]

Hi guys,

I have designed a low-speed SAR ADC in a 65nm CMOS. sampling speed 1MS/s. The internal clock signal was about 5MHz.

When I conduct the measurement, I found that the VDD (VDDAana, VDDdig, and VREF are all connected to the same PAD to 1.0V) changes for about 100 mV during ADC conversion.



the blue line is the VDD.

This is my second chip and I found this problem again.

Can any expert give me some opinions?? Is this normal??

thnks a lot.

 

[FvM]

VDDAana, VDDdig, and VREF are all connected to the same PAD to 1.0V

You mean, connected to one chip pad? As far as I'm aware of, that's pretty standard with low-pin-count ADCs. They are expecting bypass capacitors directly at the package pins and are probably implementing design features that reduce effects of power supply ripple on ADC performance.

At the end of the day, linearity and SNR figures will tell if the supply ripple causes a problem.

P.S.: I notice that your previous post shows multiple supply/reference pins but no bypass capacitors.

https://www.edaboard.com/threads/250159/
https://www.edaboard.com/threads/248884/