reniflal
Newbie level 1
I have been trying to configure an ad5932 dds for a week......i could get the msb output....but i couldnt get any output from vout....i.e. i couldnt get sine/triangular wave...can u help me...i will post the code now.
:-( cAn anyone help me
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 module t1( input clk, input reset, input start, output sclk, output sdata, output ss_n, output ctrl ); reg sclk_r; reg sdata_r; reg ss_n_r; reg ctrl_r; reg [4:0]counter; reg [7:0]data_counter; reg flag; reg even; reg [63:0] data; reg [64:0] data_en; reg i; assign sclk=sclk_r; assign sdata=sdata_r; assign ss_n=ss_n_r; assign ctrl=ctrl_r; always@(posedge clk or posedge reset)//flag for transmission begin if(reset) flag<=0; else if(data_counter==8'd128)//resetting flag after configguring flag<=0; else if(start&& ~i)//once start is initiated,set flag flag<=1; end always@(posedge clk or posedge reset)//counter for baudrate begin if(reset) begin counter<=5'd0;//counter to set baud rate at 1Mhz end else if(start) begin counter<=5'd0;//counter to set baud rate at 1Mhz end else if(counter==5'd25) begin counter<=0; end else begin counter<=counter+1; end end always@(posedge clk or posedge reset)//to config only once begin if(reset) i<=0; else if(data_counter==8'd128) i<=1; end always@(posedge clk or posedge reset)//ctrl pin config begin if(reset) ctrl_r<=0; else if(data_counter==8'd130 &&(i))//after configuting , delay 1 data time and assert cntrl ctrl_r<=1; else if(data_counter==8'd131)//reset cntrl after 2 data perods ctrl_r<=0; end always@(posedge clk or posedge reset)//sclk generation begin if(reset) sclk_r<=1; else if((counter==6'd25)&&flag)//sclk generation sclk_r<=~sclk_r; else if(!flag) sclk_r<=1; end always@(posedge clk or posedge reset)// begin if(reset) even<=0; else if(counter==6'd20)//transmitting data 5 ticks before negedge of sclk even<=~even; end always@(posedge clk or posedge reset)//data counter begin if(reset) data_counter<=0; else if((counter==6'd25)&&(flag||i))//counting data transmitted data_counter<=data_counter+1; end always@(posedge clk or posedge reset)//sdata sending begin if(reset) sdata_r<=0; else if( flag&&(counter==6'd24)&&(~even))//sending serial data sdata_r<=data[63]; end always@(posedge clk or posedge reset)//shifting data begin if(reset) data<=64'h0ff3ffffcfbad000; else if((flag)&&(counter==6'd01)&&(~even))//shifting serial data data<={data[62:0],data[63]}; end always@(posedge clk or posedge reset)//ss sending begin if(reset) ss_n_r<=1; else if( (flag)&&(counter==6'd10)&&(~even))//sending slave select signal ss_n_r<=data_en[64]; else if(data_counter==129) ss_n_r<=1; end always@(posedge clk or posedge reset)//shifting ss begin if(reset) data_en<=65'h00000ffff00000000; else if(flag&&(counter==6'd01)&&(~even))//shifting slave select signal data_en<={data_en[63:0],data_en[64]}; end endmodule
:-( cAn anyone help me
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