actel flashrom configuration, simulation and read

[lsy643]

hello
I have been in big trouble in using FLASH ROM of ACTEL FPGA Proasic250 recently.
Although it seems quite simple to configure and read the FLASHROM, not only the simulation but also the application in the device can not work properly.
In the simulation, whatever I do can not bring out some result. The data out from the flashrom module is always red.
Besides, after the configuration in the actgen, the content of the mem file does not change at all. Is that is right?
The file about generating and control the flash rom is in the accessory.
I am looking forward for your help.

PS(source code):


module GetNumFROM(clk_48M,clk_1HZ,outData);
//////////////////////////////////////////////
//define the IO
/////////////////////////////////////////////
//clock
input clk_48M;// drive the FLash ROM
input clk_1HZ;// generate the caculate clock
//data
output [15:0] outData;
//////////////////////////////////////////////
//define the middle varibles and parameters
/////////////////////////////////////////////
//control the FROM;
reg [6:0] flash_add;
reg [7:0] high_eight;


//////////////////////////////////////////////
//generate the FLASH
/////////////////////////////////////////////
initial
begin
flash_add<=7'd0;
high_eight<=7'd0;
end

FROM_0_9 FROM_0_9_U1(
//input
.CLK(clk_48M),
.ADDR(flash_add),
//output
.DOUT(outData[7:0])
);
assign outData[15:8]= high_eight;

//////////////////////////////////////////////
//control the output number
/////////////////////////////////////////////
always@(posedge clk_1HZ)
begin
if(flash_add==7'b0001010)
flash_add<=7'd0;
else
flash_add<=flash_add+7'd1;

end

endmodule