Accessing Micron PSRAM on Nexys 3

[Leep]

I've been reading the Micron **broken link removed** on their MT45W8MW16 70ns PSRAM over and over and over, searching Google for any type of examples, making TONS of notes, and I'm going cross-eyed trying to understand it fully. It should be fairly simple to do synchronous read/write from/to the PSRam, right? Normally I'm pretty quick at picking up on how to do things from manuals and Google searching, but this is just evading my comprehension. I feel I understand it MUCH MUCH better now than, say, 2 or 3 days ago, but I'm still not grasping it deeply enough to be able to make a simple Verilog test that simply writes some values out to RAM (addresses 0 - 256) and lets you retrieve them by setting the address (0-256) on the 8 switches and hitting a button to show the lower 8 bits of the value at that address on the LEDs.

I'm very confused on the difference between synchronous and asynchronous access. From what I understand, in asynchronous mode access is 70 ns which is ~14MHz, and in synchronous mode access can be up to 80MHz (according to the Nexys 3 ref manual). Since my primary interest at the moment is for video ram, I need to access it at 25+MHz, so I'm guessing I need to use synchronous mode.

I understand the contents of the RCR and BCR registers fairly well now, but I'm not clear on how to actually read/write them. There's a Latency (Initial & Counter) in the BCR that seems to control how many clock cycles after you initiate the Read/Write operation (when ADV/WE activates?) the data will be available on DQ. Since this deals with clock cycles, I assume it's for synchronous access.

By default though, the PSRam is in asynchronous mode, so the first thing I need to do is put it in synchronous mode right? Which involves setting BCR[15] to 0 (Synchronous), and BCR[2:0] to the Burst Length... Do I read BCR first, set the bits, then write BCR so I'm only changing those bits? And I have to do this write asynchronously, but as soon as I do then I have to use synchronous means to do any further reads/writes?

Any pointers/tips would be greatly appreciated. I feel like I'm right on the verge of all of this making sense (it doesn't help that I just started learning digital circuit design, FPGAs and Verilog about a month ago). If anyone has any example code (Verilog preferably, but I'll figure out VHDL if that's what it takes) for writing asynchronously to BCR and doing synchronous read/write bursts, that may help all this click into place.

P.S. I have checked out the opb_psram_controller from OpenCores, but that just confused me even more. It had ports (in and out) on it's top-level "module" named DQ_I, DQ_O, DQ_T, etc., each (15 downto 0), but two are out and one is in. There are only 15 DQ pins in the .UCF... I'm seriously missing something here. :|

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Lee

 

[mrflibble]

I'm very confused on the difference between synchronous and asynchronous access. From what I understand, in asynchronous mode access is 70 ns which is ~14MHz, and in synchronous mode access can be up to 80MHz (according to the Nexys 3 ref manual). Since my primary interest at the moment is for video ram, I need to access it at 25+MHz, so I'm guessing I need to use synchronous mode.

AFAIK, in asynchronous mode the device is still operating synchronously internally. Think of it as a wrapper that takes your async requests, does the necessary internal work, does internal synchronous requests, and presents you with the output. Similar to the bit of extra logic that does the refreshes for you, instead of you having to do the refresh.

Also, that PSDRAM is the same as used on the older Nexys2. Maybe you can use that fact to find some more info/example code.

 

[Leep]

Ok, I'm going to do something I don't normally do. I'm admitting defeat. I've spent over a week now trying to figure this PSRam access out and it's simply eluding me. Can someone that has a Nexys 3 (or Nexys 2) please throw together a simple synthesizable demo using the switches/buttons as input and LEDs as output to show how to store and retrieve words from the PSRam in synchronous burst mode? Maybe something as simple as: Button 1 stores 4 words (hard-coded in the HDL) in address 0 - 3, Button 2 stores 4 different words in addresses 0-3, switches 0-1 select address 0-3 and buttons 3/4 show the lower/upper 8 bits of the word at the selected address on the LEDs... Something that shows how to put the PSRam in synchronous mode, and write to and read from memory in bursts... Verilog is what I'm familiar with, but at this point I'll figure VHDL out if that's what I get. I swear, once I figure this out and the lights come on in my head about how this works, I'm going to post a how-to somewhere on this. Thanks in advance to any who can help!

 

[mrflibble]

You could try and take a look at this EDK demo project for the Nexys 2:

**broken link removed**

"EDK project that demonstrates how to connect the BSB shared buses through I/O multiplexers, allowing access to both RAM and FLASH memories on the Nexys2-500. Made using EDK 11."

Maybe that contains some puzzle pieces you're missing.

 

[rberek]

And Micron's Verilog model for that memory can be found **broken link removed**. Its under the Sim Models tab. Perhaps reverse engineering their model will help you develop yours.

I have to say that you have quite a learning curve ahead of you given you are tackling this only a month after taking up digital design ,FPGAs and HDLs...

r.b.

 

[Leep]

@rberek: That's been a major help to me throughout this whole experience; that and the **broken link removed** document from the documents tab on that same page. I think I understand from a higher level WHAT I need to do (thanks to those verilog files and that pdf), just not quite HOW to do it, or enough of the lower level details of the WHAT. I do feel that it's my extreme newness to the whole field that is hampering me the most now. It's a bit overwhelming, since a little over a month ago I didn't know what an FPGA was much less what PSRam was, and I had only a vague idea of digital circuit design. . I was doing great, at "full steam ahead" until I hit the PSRam. It's been like a brick wall to my learning. Grrrr. And it's something I need to continue with anything more advanced than simple circuits (need it for VGA memory, instruction/data RAM for CPU, etc). I suspect I just need to step away from it for a bit and come back again later with a fresh mind.

@mrflibble: <shock> I think that's new (to me)... I thought I had exhausted about all I could find via google... Can I asked what your process was to find that (might open new paths/ideas for me in my searching)? Or did you just know where to look for it? I will definitely pour over that and see if it holds any "golden nuggets". Thanks! :-D

 

[mrflibble]

Well, personally I remembered it from earlier on. But the way you could have found it is: me mentioning earlier on that this chip is also on the Nexys2, and then you looking at the **broken link removed**. It's at the bottom, in the list of support documents.

But don't feel bad about not figuring this one out right away. It seems that memory interfaces are not exactly the easiest thing around. An easy to work with module for the PSDRAM on the Nexys2 is still on the nice-to-have list. It's just not very high priority right now since all the things I do with the nexys2 I can do using block ram.

 

[Leep]

@mrflibble: That EDK Project may have been something I ran across before after all. It's c code that compiles down to code that runs on MicroBlaze, and seems to not have much code in the zip file at all. Mainly calls library routines (like XUtil_MemoryTest32) that I assume come from some Development Kit I either don't have, or haven't looked into how to generate. But I'm not sure software access to the PSRam is going to help me. It's the timing and how to implement that aspect of it at the hardware level that seems to have been confusing me the most.

But not to despair, I think it's stating to click in my head... slowly... In asynchronous mode I simply have to keep track of how much time has passed myself after initiating a read or write. There's no signal that goes high/low when the data's ready (or written). That's what's confused me the most up until now. I couldn't figure out how the PSRam let me know the data's ready... it doesn't, at least not in async mode.

In sync mode, however, it's all clock driven. Much more orderly and my mind likes it much better. The problem is I have to deal with async to initialize the PSRam into sync mode if I understand it correctly. I think I understand it enough now to start playing with some Verilog code. I just have to keep in mind that every click of a 100MHz clock is 10 ns and the PSRam needs 70ns before the data is ready. So on the 7th clock tick after initiating the read, the data should be available (or should have been written). I think I can even monitor the WAIT signal to know exactly when the data is ready. Sounds good? We'll see.

 

[johnsean.wu]

Now I'm doing the same work to you.
The PSRAM problems has puzzled me about a month.
Have you worked out ?:?:

 

[Leep]

Not yet, but I'm getting close. I played with it a bunch tonight and thought I had what should work, but I'm getting slightly different values back from the addresses I wrote to (async). The upper byte is correct, but the lower byte is wrong. I think there's a signal I have to toggle for a certain amout of time between writes. I'll play with it more tomorrow night. I'm not one to give up easily, so I'll eventually figure it out. If you have any breakthroughs, please post them here.

 

[johnsean.wu]

First I load the BCR (async),then I want to read out BCR,RCR,DIDR ,but it's not successful .where are the fault ,I don't know~

 

[numericys]

First I load the BCR (async),then I want to read out BCR,RCR,DIDR ,but it's not successful .where are the fault ,I don't know~

Maybe you can try this little piece of code. I wrote it to verify that the PSRAM is working. It works on the Nexys 3.

 

[johnsean.wu]

Maybe you can try this little piece of code. I wrote it to verify that the PSRAM is working. It works on the Nexys 3.

thanks a lot firstly, but how can I get the code ?

 

[numericys]

I think you have to be logged in. Do you see the attached file : psram_reg_read.zip‎ ?
The code is very simple and not optimized. I've translated the datasheet timing into a state machine. It displays the BCR lower byte on the leds.

 

[RWTH]

I think you have to be logged in. Do you see the attached file : psram_reg_read.zip‎ ?
The code is very simple and not optimized. I've translated the datasheet timing into a state machine. It displays the BCR lower byte on the leds.

Hello everybody!
Doing the same thing at the moment :*)
I also cannot see the mentioned file, though I'm definetely logged in.
maybe you could repost that file?
Thanks