v_suma
Newbie level 4
Hi,
I am interested in knowing how the absolute value of a complex number can be found using digital logic design.
I know that abs(x+iy) = sqrt(x^2 + y^2).
Is there any easy way to implement it in Verilog or VHDL?
I am interested in knowing how the absolute value of a complex number can be found using digital logic design.
I know that abs(x+iy) = sqrt(x^2 + y^2).
Is there any easy way to implement it in Verilog or VHDL?