asicgiga
Newbie
When developing new semiconductors, corner lots are sometimes performed.
However, just as the process of the TT target forms a spread containing SS, TT, FS, SF,
the corner lot will also form a new spread that is not in the process library. (outer range from process model library)
Then, it is expected that chips from corner lot are differ from the process model used during design, and it will be uncertain whether they will operate.
Can you explain in detail the analysis process performed through corner lot?
And another question, is it possible to mass produce it as a shifted process? (e.g. shifting to FF is helpful for timing margin)
However, just as the process of the TT target forms a spread containing SS, TT, FS, SF,
the corner lot will also form a new spread that is not in the process library. (outer range from process model library)
Then, it is expected that chips from corner lot are differ from the process model used during design, and it will be uncertain whether they will operate.
Can you explain in detail the analysis process performed through corner lot?
And another question, is it possible to mass produce it as a shifted process? (e.g. shifting to FF is helpful for timing margin)