about moscap decouple

[test_123]

In general, in the chip spare space we add moscap(gate connect to one power rail, and source-drain connect to the other power rail) for decoupling as moscap has most unit capacitor? but someone said it has esd issue as the gate connect to power rail? then how should we do? thanks!

 

[ranier]

if you concern about esd , you add a small resistor(10 ~ 20 ohm) between power line and mos gate.

but I think, gate connected power lline doesn't make esd problem above 0.18um ( this is real problem 0.13um and nano-meter tech)

 

[electronspin]

what supply are you using for what minimum length transistor?

This is fine for the thicker oxide 2.5->3.3v fets. Do it all the time, no problems, no esd issue (although the chip itself does have esd protection).

If you examine these caps you will see that there does exist a distributed resistance which means you should actually simulate with it in mind. I have run into the case where without meaning to the series resistor is actually too large and the capacitor is useless at the frequencies its supposed to help out. So, um, watch out for that.

If you have .15u or lower thin oxide fets (digital) as your power decoupling caps you will notice the start of leakage (at .15u and painful leakage below). If you are using thin oxide fets(normally used for 1v supplies) on a thick oxide supply domain (normally 2.5-3.3v) then you have problems.

 

[ESDSolutions]

It is indeed typical practice to fill empty space in the IC with decoupling capacitance. Because it has the highest capacitance per silicon area, thin oxide is used a lot. It does create an ESD (and leakage too) issue because a thin oxide has a low transient breakdown value certainly from 130nm technologies. If the core power-ground ESD protection clamp is designed properly and distributed according to the rules specified then there should be no problem. However, if you use this thin oxide capacitance (1.2V device) in a thick oxide domain (e.g. 3.3V IO / analog domain) then the standard (foundry supplied) ESD protection clamp might not be effective. Proprietary solutions exists