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about mixed singal simulation

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cirand

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how to watch an internal node voltage waveform of a verilog module when I run mixed singal simulation by spectreVerilog?
 

the simplest method is in the in the simulator option, choosing probe all the nodes.
 

choosing probe all will do save all the node but not save verilog module internel node.
and also, save all will generate a huge file that exceed 2G for my simulation.
 

why dont u make tht internal node as one output pin which you dont connect to any other node or terminate with high resistor value for simulation.
 

yes,i have ever do it as you say, but it is much not convenience to debug the circuit.
 

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