a very silly question but just come to my mind

[hearter]

in a PLL design, you have PFD, meaning PD and FD, I have been doing PLL for over 10 years now, but never tried to simulate freq capture and phase capture seperately, sth came to my mind when I was reading a board message, that it is possible PLL will lock to certain frequency, but phase detection is not working for the PFD, meaning you may have high jitter but correct freq. anyone can share how do you simulate the phase locking range of the PFD? assume a tristate regular textbook PFD w/o dead zone.

thanks

Heart