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Lets see do I interpret your question correctly. When there is 500mA of current flow out from the LDO at Vout = 1V, I guess the current flowing into the LDO at the Vin pin will be 500mA too. Therefore, the power efficiency of LDO is:
Efficiency = Pout/Pin ~ 1.0V x 0.5A / 5.0V x 0.5A = 20%
That is a proof that LDO is relative lossy comparing with switching power converter. Moreover, that is also why people would like to reduce the dropout voltage (e.g. different between Vin and Vout for minmiizing power loss).
1) The meaning of "Low dropout" is the difference between Vin and Vout?
or the source resistance of voltage source is small despite the loading
sinks large current suddenly?
Anybody can tell me what's the correct definition of "LDO"?
2) Why the efficinecy is so bad such as 20%?
3) Often, what's the efficiency of LDO? For example, 3V to 1V.
Added after 3 minutes:
scottieman said:
hebu said:
If the Vin=5V, and LDO out=1V.
In addition, the LDO out curent=500mA. Does it mean the current into
the regulator is 100mA?
Lets see do I interpret your question correctly. When there is 500mA of current flow out from the LDO at Vout = 1V, I guess the current flowing into the LDO at the Vin pin will be 500mA too. Therefore, the power efficiency of LDO is:
Efficiency = Pout/Pin ~ 1.0V x 0.5A / 5.0V x 0.5A = 20%
That is a proof that LDO is relative lossy comparing with switching power converter. Moreover, that is also why people would like to reduce the dropout voltage (e.g. different between Vin and Vout for minmiizing power loss).
1) The meaning of "Low dropout" is the difference between Vin and Vout?
or the source resistance of voltage source is small despite the loading
sinks large current suddenly?
Anybody can tell me what's the correct definition of "LDO"?
Dropout voltage is the source-to-drain voltage (if MOSFET is used) or the emitter-to-collector voltage (if BJT is used) of the power transistor when it is delivering maximum current to the load.
Since LDO is a series regulator, it means the power transistor to deliver current to the load is in between the supply voltage and the load. In other words, the current passing through the power transistor is almost the same as the current passing through the load. Hence, the input power will be ~ Vin*Iin, and output power is Vout*Iout. As mentioned before, Iin ~ Iout, power efficiency will be Vin/Vout. So, the large the voltage difference between Vin and Vout, poor the efficiency it is.
hebu said:
3) Often, what's the efficiency of LDO? For example, 3V to 1V.
I am also totaly confused about the disccusion above!!!!
LDO is a low-dropout regulator!! That means in the case a battery of lets say provides 1.25 the output voltage can be as high as 1.2 Volts! In your discussion above I realy don't understand the following: Input current of 100mA!!! and output 500mA??!!!. Since usually boosted nmos or pmos are used, the current flowing into drain is the same flowing out of the drain. So, there is something wrong with your considerations. Without caps or inductors you will not be able to achieve a "transormation" - but this is not a ldo, it is called swithed supply.
However, the example with 5V in, 1V out --> so the series transistor has a Vds of 4V, 500mA output --> 2W are dissipated by the ldo, the output power is 500mW and 2.5W have to be delivered by the 5V supply. So you will get an efficency of 0.5W/2.5W = 20%. But the input current is approximately also 500mA and not 100mA!!!
Forgive my big mistake. I don't really know the power electronics.
First, I guess the purpose of regulator is to transform the voltage of
battery from high to low so as to apply a correct voltage to the circuit.
Such as the chip designed in deep-submicron cmos, which we need to
apply a quite low voltage different from system power. Definitely, it's
not a efficient way to perform this.
By the way, why we need LDO regulator rahter than connecting
the battery to the functional circuit directly, since we want to make
a low "dropout" voltage?
However, the example with 5V in, 1V out --> so the series transistor has a Vds of 4V, 500mA output --> 2W are dissipated by the ldo, the output power is 500mW and 2.5W have to be delivered by the 5V supply. So you will get an efficency of 0.5W/2.5W = 20%. But the input current is approximately also 100mA and not 500mA!!!
However, the example with 5V in, 1V out --> so the series transistor has a Vds of 4V, 500mA output --> 2W are dissipated by the ldo, the output power is 500mW and 2.5W have to be delivered by the 5V supply. So you will get an efficency of 0.5W/2.5W = 20%. But the input current is approximately also 100mA and not 500mA!!!
Not only do we need to provide a stable voltage due to loading conditions, but different chips are made from different processes and can only tolerate certain voltages (0.18um vs. 0.8um BCD).
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