a simple cpu in verilog

[sepehroo]

Hey guys , please help me here, I'm so close to bang my face against the wall!
I'm trying to implement a very simple CPU using verilog. the datapath is attached to this post.

and here are my modules:

module tri_8bits(input_stream, control_signal, output_stream);
input [7:0] input_stream;
input control_signal;
output [7:0]output_stream;
assign output_stream = control_signal? input_stream: 8'bZZZZZZ;
endmodule

module tri_6bits(input_stream, control_signal, output_stream);
input [5:0] input_stream;
input control_signal;
output [5:0]output_stream;
assign output_stream = control_signal? input_stream: 6'bZZZZZZ;
endmodule

module pc_holder(input_stream, ld, inc, clr, output_stream,clk,rst);
input [5:0] input_stream;
input ld,inc,clr,clk,rst;
output reg [5:0] output_stream;
always @(posedge(clk) or negedge(rst))
	begin
		if (rst==0)
			output_stream=6'b00000000;
		else if (clr==1)
			output_stream=6'b00000000;
		else if (ld==1)
			output_stream=input_stream;
		else if (inc==1)	
			output_stream=input_stream+1;
	end	
	
endmodule

module alu(a, b, pass, add,q);
input [7:0] a;
input [5:0] b;
input pass,add;
output reg [7:0] q;
always @(pass or add) //vaghty shart barghar bood varede badane sho
	begin		
		q=8'b00000000;
		if (pass==1)
			q=a;
		else if (add==1)
			q=a+b;

	end		

endmodule

module Dcontroller(opcode, rd_mem, wr_mem, ir_on_adr, pc_on_adr, dbus_on_data, data_on_dbus, ld_ir, ld_ac,
					ld_pc, clr_pc,inc_pc, pass, alu_on_dbus, add,clk,rst);
					
input clk,rst;
input [0:1] opcode;
output reg rd_mem, wr_mem, ir_on_adr, pc_on_adr, dbus_on_data, data_on_dbus, ld_ir, ld_ac,
					ld_pc,inc_pc, clr_pc, pass, alu_on_dbus, add;					

parameter [1:0] reset=0, fetch=1, decode=2, execute=3;
reg [1:0] current;



always @(posedge(clk) or negedge(rst))
begin	
	if (rst==0)begin
			rd_mem <= 1'b0;
			pc_on_adr <= 1'b0;
			pass <= 1'b0;
			ir_on_adr <= 1'b0;
			wr_mem <= 1'b0;
			ld_ac <= 1'b0;
			dbus_on_data <= 1'b0; 
			data_on_dbus <= 1'b0;
			ld_ir <= 1'b0; 
			alu_on_dbus <= 1'b0;
			add <= 1'b0;
			inc_pc <= 1'b0;
			clr_pc <= 1'b0;
			ld_pc <= 1'b0;
			current<= reset;
	end
	else
	case (current)
		reset: begin
			clr_pc<= 1'b1;	
			current<= fetch;		
		end
		fetch: begin					
			
			pass <= 1'b0;
			ir_on_adr <= 1'b0;
			wr_mem <= 1'b0;
			ld_ac <= 1'b0;
			dbus_on_data <= 1'b0; 						 
			alu_on_dbus <= 1'b0;
			add <= 1'b0;			
			clr_pc <= 1'b0;
			ld_pc <= 1'b0;
			
			pc_on_adr<=1'b1;
			rd_mem<=1'b1;
			data_on_dbus<=1'b1;
			ld_ir<=1'b1;
			inc_pc<=1'b1;
			current<= decode;
		end
		decode: begin
			current<= execute;
		end	
		execute: begin
			/*
			ld_pc<=1'b1;
			ir_on_adr<=1'b1;
			dbus_on_data<=1'b1;
			ld_ac<=1'b1;
			alu_on_dbus<=1'b1;
			wr_mem<=1'b1;
			*/						
			case (opcode)
				2'b00:begin
					ir_on_adr<=1'b1;
					data_on_dbus<=1'b1;
					ld_ac<=1'b1;
					rd_mem<=1'b1;
				end
				2'b01:begin
					 wr_mem<=1'b1;
					 pass<=1'b1;
					 alu_on_dbus<=1'b1;
					 dbus_on_data<=1'b1;
					 ir_on_adr<=1'b1;
				end
				2'b10:begin
					ld_pc<=1'b1;
				end
				2'b11:begin
					add<=1'b1;
					alu_on_dbus<=1'b1;
					ld_ac<=1'b1;
					data_on_dbus<=1'b0;
					dbus_on_data<=1'b1;					
				end	
			endcase	
			current<= fetch;
		end			
	endcase	
	

end

endmodule

module my_registers8bit(input_stream, output_stream,clk, ld);
input [7:0] input_stream;
input clk;
input ld;
output reg [7:0] output_stream;
always @(posedge(clk))
	begin
		if (ld==1)
			output_stream=input_stream;   //nonblocking
	end	
	
endmodule

module IR(input_stream, clk, ld, opcode, output_stream);
input [7:0] input_stream;
input clk;
input ld;
output reg [5:0] output_stream;
output reg [1:0] opcode;

always @(posedge(clk))
	begin		
		if (ld==1)
			begin
				output_stream=input_stream[5:0];								
				opcode=input_stream[7:6];
			end
		
	end	
	
endmodule

module my_registers8bit(input_stream, output_stream,clk, ld);
input [7:0] input_stream;
input clk;
input ld;
output reg [7:0] output_stream;
always @(posedge(clk))
	begin
		if (ld==1)
			output_stream=input_stream;   //nonblocking
	end	
	
endmodule

and finally the top module:

module project4(data_bus,clk,rst, addr_bus,rd_mem, wr_mem);


inout [7:0] data_bus;
output rd_mem, wr_mem;
wire [1:0]opcode;
output [5:0] addr_bus;
wire [7:0] dbus;
input clk,rst;
wire ld_ac, ld_ir, inc_pc,ld_pc,clr_pc, pass, add,data_on_bus, 
	dbus_on_data,alu_on_dbus, ir_on_add, pc_on_add;
wire [5:0] ir_output, pc_output;
wire [7:0] alu_output,ac_output ;


tri_8bits tri_A(data_bus, data_on_bus, dbus);

my_registers8bit AC(dbus, ac_output, clk, ld_ac);

IR my_ir (dbus, clk, ld_ir, opcode, ir_output);


Dcontroller controller(opcode, rd_mem, wr_mem, ir_on_add, pc_on_add, dbus_on_data, data_on_bus, ld_ir, ld_ac, ld_pc,
clr_pc,inc_pc, pass, alu_on_dbus, add, clk, rst);


pc_holder pc(ir_output, ld_pc, inc_pc, clr_pc, pc_output,clk,rst);

tri_6bits tri_E(pc_output, pc_on_add, addr_bus); //add this later
tri_6bits tri_D(ir_output, ir_on_add, addr_bus); //add this later



alu my_alu (ac_output, ir_output, pass, add, alu_output);

tri_8bits tri_C(alu_output, alu_on_dbus, dbus);
tri_8bits tri_B(dbus, dbus_on_data, data_bus); 

endmodule

the problem is that when I'm trying to simulate it using the simulator tool, when assigning some value to data_bus it will be shown as some crossed line as if the value is HiZ there.
I'm a real newbie to verilog, please tell me how can assign values to my data_bus (which is an inout port)

PS: there is no memory unit yet, I will manually give values to data_bus