bestwang
Newbie level 3
I am reading SMBus spec2.0 and I cannot understand a timing requirement:
In SMBus spec 4.3.1, it is about clock synchronization, it says the interval between the first high to low transition of CLK1 and CLK2 must be less than Tlow:min-Tsu:dat. I cannot understand why it is specified here?
In SMBus spec 4.3.1, it is about clock synchronization, it says the interval between the first high to low transition of CLK1 and CLK2 must be less than Tlow:min-Tsu:dat. I cannot understand why it is specified here?