a querstion for Chip design

[amphy]

Hi,

Would you please tell me how I design and make the boundary pad around the
chip using Cadence SOC Encounter and simulate and verify the design to be a
practical chip picture in my computer,thank you!

 

[amphy]

Re: a question for Chip design

Hi,

Who know how to design and make the Wire-BOUND PAD around a chip using
Cadence SOC Encounter software,thank you!