A problem in a PLL circuit [hlp]

[No one]

Hello Everyone;
I have designed a fractional PLL circuit using ADF4156 of Analog Devices, but it has two problem:
1) It has two spurs about ±25kHz apart from the desired carrier that are about 20-30dBc below carrier.
2) It's lock time isn't good.
Please help me.

 

[kspalla]

Please share the schematic design
What is the step size? Ref Oscillator frequency? If possible give us the complete details.