A problem about PLL constructed by veriloga

[icsoul]

veriloga loop filter

When constructing a pll with veriloga, I got the vco control voltage like in the attachment. It seems to be oscillating periodically.


Which block has problem according the vctrl waveform?

 

[sparso]

Loop filter.

 

[LvW]

Yes, most probably the loop filter is not design properly - and the closed loop oscillates.
The loop filter not only has to suppress some unwanted spurious signals but it is responsible for the dynamic behaviour of the whole system.
Normally, the loop filter will be first order with a zero .
Try to scetch the BODE diagram for the loop gain and check if it crosses the 0-dB line with a slope of roughly -20 dB/dec.

 

[icsoul]

I have known the problem.

The control voltage of VCO was connected to the capacitor, changed it to resistor of LP. Everything is ok.