A good hardware verification language

[vipinlal]

I know VHDL and would like to learn a hardware verification language.I googled and found that these are the common languages used right now: SystemVerilog, OpenVera, e, and SystemC.

So right now I am confused about learning which one among the ones listed above.I searched here and found this link:
https://www.edaboard.com/threads/34629/
But this was 5 years before and the situation may have changed a lot by now.

My question is which verification language is most used in the industry to test the HDL design in the functional level?
I hope that all HVL's are capable of testing the design even if the design is made in VHDL or in Verilog.

Please guide me...

 

[AdvaRes]

The same languages are used today in industry. If your design is made in VHDL or Verilog go for e Language or SystemVerilog

 

[vipinlal]

which simulator should I use for system verilog and E language?
Is it possible to get a free compiler+simulator for these languages? I meant something like Xilinx Webpack edition where you get almost all the features required for HDL design.

 

[AdvaRes]

ModelSim, Questasim for SystemVerilog and Specman for E.

 

[TrickyDicky]

Modelsim does SystemC as well.

 

[vipinlal]

i have downloaded ModelSim SE version. Will it support the basic capabilities of system verilog and system C.

Also how does E varies from system verilog and system C?

 

[ran_shani]

As far as I know , there are two main HW verification languages: systemverilog and e language .
E language with specman tool was the leading one for several years but nowadays systemVerilog become more and more popular.
In my opinion, systemVerilog is more intuitive for those how knows verilog and understand the object oriented concept.

Br,

Ran Shani