Fuzail Hussain
Newbie level 5
Iam trying to simulate 8 transistor fulladder circuit in DIGITAL SCHEMATIC.
If someone could check if the circuit is rightly constructed because it is not satisfing the logic of full adder
![Picture4.png Picture4.png](https://www.edaboard.com/data/attachments/17/17372-40d0d8a56a90e42965b87b6e799ec744.jpg)
![Picture2.png Picture2.png](https://www.edaboard.com/data/attachments/17/17371-de4ce74d196fb99add32adb7b40310b3.jpg)
the circuit is designed in digital schematic and its paper diagram is also given
I don't find any fault in circuit construction but the output isn't satisfying the full adder truthtable.
Could anyone pls find out a solution.
Regards,
FUZAIL HUSSAIN S.
If someone could check if the circuit is rightly constructed because it is not satisfing the logic of full adder
![Picture4.png Picture4.png](https://www.edaboard.com/data/attachments/17/17372-40d0d8a56a90e42965b87b6e799ec744.jpg)
![Picture2.png Picture2.png](https://www.edaboard.com/data/attachments/17/17371-de4ce74d196fb99add32adb7b40310b3.jpg)
the circuit is designed in digital schematic and its paper diagram is also given
I don't find any fault in circuit construction but the output isn't satisfying the full adder truthtable.
Could anyone pls find out a solution.
Regards,
FUZAIL HUSSAIN S.