8 bit multiplier by verilog

[hodagh]

Hi everyone
I wrote a behavioral verilog code for an unsigned 8*8 multiplier but when I simulate it, it doesn't show the right answer
I would be happy if anybody can help !

module mult8(p,x,y);
output [15:0]p;
input [7:0]x,y;
reg [15:0]p=0;
reg [7:0]a;
integer i;

always @(x , y)
begin
a=x;

for(i=0;i<8;i=i+1)
begin
if(y)
begin
p<=p+a;
a=a<<1;
end
else
a=a<<1;

end

end

endmodule

 

[FvM]

What do you expect when left-shifting an 8-bit value? The size isn't increased above 8 bits.

 

[hodagh]

What do you expect when left-shifting an 8-bit value? The size isn't increased above 8 bits.

I wanted to implement the normal way of multiplying
with for loop I check multipliers bits : 1- if it's 1 add multiplicand to product and left shift the multiplicand 2-if it's 0 just shift

 

[FvM]

Yes, but the shifted variable must be extended to 16 bit size.

 

[hodagh]

Yes, but the shifted variable must be extended to 16 bit size.

thanks for the point
but still when I give the random numbers of x=4 and y=5 in active hdl the product will be A01B

 

[FvM]

Yes, there are more errors

module mult8(p,x,y); 
output [15:0]p;
input [7:0]x,y; 
reg [15:0]p;
reg [15:0]a;
integer i; 

always @(x , y)
begin 
  a=x;
  p=0; // needs to zeroed
  for(i=0;i<8;i=i+1)
  begin
    if(y[i])
      p=p+a; // must be a blocking assignment
    a=a<<1;
  end
end
endmodule

P.S.: A brief compare of your mutiplier implementation with a default synthesis tool inferred multiplier (p = x*y), disabling hardware multipliers:

Altera Cyclone III
design mult8 p=x*y
LEs 132 102
tpd 23.6 13.7 ns

 

[hodagh]

I didn't get your p.s. !
but I attached the resulting simulation

 

[FvM]

I didn't get your p.s.

It says, that you get about double speed with less logic cells just writing p=x*y