ABHISEK SINGH
Newbie
Hey FOLKS, can anyone assist me with performing READ, WRITE and DELAY of a 6T-SRAM cell in CADENCE VIRTUOSO 45nm CMOS technology.
I designed below test schematic and generated HSPICE netlist but confuse in how to modify the netlist in order to perform READ, WRITE and DELAY operations.
Kindly assist here.
I designed below test schematic and generated HSPICE netlist but confuse in how to modify the netlist in order to perform READ, WRITE and DELAY operations.
Kindly assist here.
