4T SRAM resistance value

[vnramkrishnan]

hi,

what is the typical 4T SRAM load resistance value connected to NMOS1 and NMOS2 drain

tnx

 

[rosaeidi]

Hi

The values of RL must be as high as possible to retain a reasonable noise margin. NML, i.e., to limit the “0” level rise and reduce the static power consumtion.

The lower limit on RL is set by the required noise immunity and power consumption requirements. The upper resistance limit on RL is set by the requirement to provide a pull-up current of at least two orders of magnitude larger than the leakage current.

See:
M. Rabaey, A. Chandrakasan, and B.Nikolic, "Digital Integrated Circuits, A Design Perspective," 2nd Edition, Prentice Hall, ISDN 0-13-090996-3, 2003.

Rosa