diju.ms
Newbie level 5
what will happen if i am using two if-end if blocks inside a process in vhdl??it will be executed sequntially or parallelly??
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its a program of 16 byte ram..but when i am giving clock output lags by one clock...so its almost like two separate blocks working parallel
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Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity RAMO is PORT(ADDRESS:IN STD_LOGIC_VECTOR(3 DOWNTO 0); WR:IN STD_LOGIC:='1'; CLK:IN STD_LOGIC; DATAIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0):="10101010"; DATAOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY; architecture Behavioral of RAMO is TYPE TEMPRAM IS ARRAY (0 TO 15) OF STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL TEMP:TEMPRAM; SIGNAL I:INTEGER:=0; BEGIN PROCESS(CLK,ADDRESS) BEGIN IF(CLK'EVENT AND CLK='1')THEN IF(ADDRESS="0001")THEN I<=1; ELSIF(ADDRESS="0010")THEN I<=2; ELSIF(ADDRESS="0011")THEN I<=3; ELSIF(ADDRESS="0100")THEN I<=4; ELSIF(ADDRESS="0101")THEN I<=5; ELSIF(ADDRESS="0110")THEN I<=6; ELSIF(ADDRESS="0111")THEN I<=7; ELSIF(ADDRESS="1000")THEN I<=8; ELSIF(ADDRESS="1001")THEN I<=9; ELSIF(ADDRESS="1010")THEN I<=10; ELSIF(ADDRESS="1011")THEN I<=11; ELSIF(ADDRESS="1100")THEN I<=12; ELSIF(ADDRESS="1101")THEN I<=13; ELSIF(ADDRESS="1110")THEN I<=14; ELSIF(ADDRESS="1111")THEN I<=15; ELSE I<=0; END IF; IF(WR='1')THEN TEMP(I)<=DATAIN; ELSE DATAOUT<=TEMP(I); END IF; END IF; END PROCESS; END BEHAVIORAL;
its a program of 16 byte ram..but when i am giving clock output lags by one clock...so its almost like two separate blocks working parallel
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