[SOLVED] 16 qam modulation in spartan3e

[panos_papajohn]

Hello everyone

I want to implement a simple OFDM modulator. It ll be consisted of a 16 QAM block and a FFT block. I think the QAM is pretty simple. I used a case statement to map the input bits to integer values. I want to convert this integer to std_logic_vector so i used the to_signed function to convert the integer to a signed value and then I am using the to_stdlogicvector to convert it to the desired type. When I compile the code (Xilinx 13.1) I get the following error
**broken link removed**

Below is my code. Its just an 16 QAM symbol mapper :

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;



-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity qam16 is
Port ( data : in STD_LOGIC_VECTOR (3 downto 0);
Re_part : out STD_LOGIC_vector(7 downto 0);
Im_part : out STD_LOGIC_vector(7 downto 0);
clock : in STD_LOGIC);
end qam16;

architecture Behavioral of qam16 is
signal Q : integer range -2 to 2;
signal I :integer range -2 to 2;
signal Qsigned :signed (7 downto 0);
signal Isigned :signed (7 downto 0);
begin
process(clock)
begin
if (clock'event and clock ='1')
then
case data is
when "0000" => Q<= -1;
I<=-1;
when "0001" => Q<= -2;
I<=-1;
when "0010" => Q<= -1;
I<=-2;
when "0011" => Q<= -2;
I<=-2;
when "0100" => Q<= 1;
I<=-1;
when "0101" => Q<= 2;
I<=-1;
when "0110" => Q<= 1;
I<=-2;
when "0111" => Q<= 2;
I<=-2;
when "1000" => Q<= -1;
I<=1;
when "1001" => Q<= -2;
I<=1;
when "1010" => Q<= -1;
I<=2;
when "1011" => Q<= -2;
I<=2;
when "1100" => Q<= 1;
I<=1;
when "1101" => Q<= 2;
I<=1;
when "1110" => Q<= 1;
I<=2;
when "1111" => Q<= 2;
I<=2;
when others => Q<=0; I <=0;
end case;

end if;
end process;
Qsigned <= TO_SIGNED (Q,8 );
Isigned <= TO_SIGNED (I,8 );
Re_part <= TO_STDLOGICVECTOR(Qsigned);
Im_part <= TO_STDLOGICVECTOR(Isigned);
end Behavioral;

Any ideas what I might missing? Thanks in advance
panos_papajohn

 

[TrickyDicky]

what you want to do is this:

RE_part <= std_logic_vector(Qsigned);
Im_part <= std_logic_vector(Isigned);

remove ieee.std_logic_unsigned.all from your code, you're not using it and everything you need is covered with the numeric_std library.

There is no to_stdlogicvector function in the libraries you have included.

 

[panos_papajohn]

Thank you TrickyDicky. I have seen this library in https://www.cs.umbc.edu/portal/help/VHDL/packages/numeric_std.vhd and I thought it was correct. Anyway, everything is fine now thank you again for tour help