12V to TTL S/R.... ( a new twist....)

[TheCPUWizard]

(a new twist on a common topic)..
2 wire input. Normally NC between them. Will eventually get a momentary + or - 12V differential between them.... need to set that to a Set/Reset flipflop with TTL (or 3.3V) output...
Many possible circuits, but I am going to need a dozen of these (or more) to monitor sensors - so locking for something that is fairly robust, but also minimizes complexity...

 

[KlausST]

Hi,

I don´t understand what you want us to tell.
--> please draw a sketch (schematic, voltages, ...) and ask a clear question.

Klaus

 

[BradtheRad]

RS flip-flop is akin to a logic probe, or memory cell. Of course there's the classic 2-transistor formation. We can also choose to build it from logic gates:

* buffer gate with hysteresis
* AND gate with hysteresis
* two invert-gates cross-coupled with hysteresis
* Schmitt trigger (hysteresis is built-in)

To protect the 3.3v device, drop 12v input signals to a safe level via zener diode (or led, diode string).

 

[barry]

We need a picture or something; your description makes no sense. youve got 3 input states (shorted, +12, -12) and two output states (set/reset).

maybe you need two comparators and a SR latch, i don’t know.

 

[TheCPUWizard]

RS flip-flop is akin to a logic probe, or memory cell. Of course there's the classic 2-transistor formation. We can also choose to build it from logic gates:

* buffer gate with hysteresis
* AND gate with hysteresis
* two invert-gates cross-coupled with hysteresis
* Schmitt trigger (hysteresis is built-in)

To protect the 3.3v device, drop 12v input signals to a safe level via zener diode (or led, diode string).

View attachment 178863

View attachment 178864

Thanks for the response, preparing a better set of info...

 

[TheCPUWizard]

View attachment 178875

There are 2 possibilities...
a) I1 & I2 are not connected to anything : no change to output.
b) I1 is connected to +12V relative to I2 (no relation to TTL Gnd or VCC) : Q goes positive.
c) I2 is connected to -12V relative to I2 (no relation to TTF Gnd or VCC) : Q Goes negative...
I could use a pair of complementary opto isolators (with current resistory) and then use the outputs of the opto to be the S/R of a flipflop...
That is probably package as (2 E817 opto, 3-4 current limit resistors, 1/2 of dual flipflop [Now scale up to there to 12-20 channels of this on a board and the package count is quite high....

So is there a "neat design that could drastically reduce this?

 

[barry]

View attachment 178875

There are 2 possibilities...
a) I1 & I2 are not connected to anything : no change to output.
b) I1 is connected to +12V relative to I2 (no relation to TTL Gnd or VCC) : Q goes positive.
c) I2 is connected to -12V relative to I2 (no relation to TTF Gnd or VCC) : Q Goes negative...
I could use a pair of complementary opto isolators (with current resistory) and then use the outputs of the opto to be the S/R of a flipflop...
That is probably package as (2 E817 opto, 3-4 current limit resistors, 1/2 of dual flipflop [Now scale up to there to 12-20 channels of this on a board and the package count is quite high....

So is there a "neat design that could drastically reduce this?

That’s THREE possibilities. And how can I2 be “-12V relative to I2”? Do you mean relative to I1? If so, isn’t that the exact same thing as I1 being +12 relative to I2?

 

[TheCPUWizard]

That’s THREE possibilities. And how can I2 be “-12V relative to I2”? Do you mean relative to I1? If so, isn’t that the exact same thing as I1 being +12 relative to I2?

Typo....

Imaging I1 and I2 are external lead...

Connect I1 to the + of a battery and I2 to the - : set the output
Connect I1 to the - of a battery and I2 to the + : reset the output

 

[KlausST]

Hi,

it´s all just confusing without a drawing.

Klaus

 

[TheCPUWizard]

Hi,

it´s all just confusing without a drawing.

Klaus

I uploaded a drawing earlier... black box. Two inputs I1 and I2... one output Q

 

[KlausST]

I uploaded a drawing earlier

???

 

[TheCPUWizard]

???

 

[KlausST]

Hi,

Where is 12V where TTL, where NC....?

I´ll better leave... I don´t like to beg for each detail.

Klaus

 

[barry]

Hi,

Where is 12V where TTL, where NC....?

I´ll better leave... I don´t like to beg for each detail.

Klaus

Why, it's as clear as day. There's an I1. And an I2. And a Q. And a very nice rectangle.

 

[betwixt]

In my simple mind, the problem here is "where are the voltages relative to?".
The original post states +12v or -12V difference BETWEEN them but makes no mention of where the logic output is referenced to.

For example, relative to the logic ground are they +6V and -6V, one way or the other or are they +106V and +94V or whatever.

What come to mind is if only the difference has to be detected there are only two states to consider, either there is no difference or there is one. If the voltages are suitable, a bridge rectifier will sort out any polarity issues and an attenuator may resolve the voltage levels. It could be as simple as four diodes and a couple of resistors.

If I1 and I2 are 'floating', consider dropping the voltages with a potential divider then using RS422/RS485 line receivers to look for the differential and gate their output together.

If you want to use a SR flip-flop, where does the other input come from? Detecting a voltage differential can either set or reset it but something else has to revert the state.

Brian.

 

[TheCPUWizard]

OK, so the following is a schematic that works. BUT the package count is high since I will need up to 16 of these on a single board....
So, is there an alternate circuit that would have similar functionality???

 

[betwixt]

I don't think that would work. R1 and R2 should be in the individual LED connections to U1 and U2 and one of them needs pins 1 and 2 swapping over. Also 'D' and 'C' on U3A should be tied to a logic level.
If the output voltage is at 3.3V logic level and the R/S inputs are tied to 1.5V there is a risk of false flipping.

What are the actual voltages on J1 measured to GND1 ?
Does J1 have to be isolated from the output stage?

Brian.

 

[TheCPUWizard]

I don't think that would work. R1 and R2 should be in the individual LED connections to U1 and U2 and one of them needs pins 1 and 2 swapping over. Also 'D' and 'C' on U3A should be tied to a logic level.
If the output voltage is at 3.3V logic level and the R/S inputs are tied to 1.5V there is a risk of false flipping.

What are the actual voltages on J1 measured to GND1 ?
Does J1 have to be isolated from the output stage?

Brian.

Brian, It works Just fine...

--- Updated Oct 5, 2022 ---

I don't think that would work. R1 and R2 should be in the individual LED connections to U1 and U2 and one of them needs pins 1 and 2 swapping over. Also 'D' and 'C' on U3A should be tied to a logic level.
If the output voltage is at 3.3V logic level and the R/S inputs are tied to 1.5V there is a risk of false flipping.

What are the actual voltages on J1 measured to GND1 ?
Does J1 have to be isolated from the output stage?

Brian.

Voltages on J1 are not at all related to voltages on the rest of the circuit... could be 115VAC relative riding on them... What is known, is that *if* they are momentarily connected to a source there will be a 12VDC *differential* on them of one polarity or the other. The polarity determines which way the FF latches (see all previous definitions of function).

 

[barry]

I don't think that would work. R1 and R2 should be in the individual LED connections to U1 and U2 and one of them needs pins 1 and 2 swapping over. Also 'D' and 'C' on U3A should be tied to a logic level.
If the output voltage is at 3.3V logic level and the R/S inputs are tied to 1.5V there is a risk of false flipping.

What are the actual voltages on J1 measured to GND1 ?
Does J1 have to be isolated from the output stage?

Brian

The circuit should work just fine as shown. Except 74HC logic is specified only down to 2v, not 1.5

And there are 8 and 32 opto packages. Who knows if you can find them.

But, Not-a-wizard, if you had posted your schematic in the original post instead of us having to beat it out of you, you would have a lot fewer people annoyed with you.

 

[TheCPUWizard]

there is no difference or there is one.

No, the whole purpose of the circuit is that when there is a differential to latch the direction of the differential, and maintain that state when the connections are terminated..

--- Updated Oct 6, 2022 ---

The circuit should work just fine as shown. Except 74HC logic is specified only down to 2v, not 1.5

Vcc is 5VDC so the HC is fine. Yes, pins should be tied... but none of that has anything to do with what I am asking.... Are there components I have not considered which would reduce the component count. For example, multiple opto couplers that are internally configured or have built in latches...finding a lower component, lower cost, smaller solution to my already working circuit was the reason I posted at all....

--- Updated Oct 6, 2022 ---

The circuit should work just fine as shown. Except 74HC logic is specified only down to 2v, not 1.5

Vcc is 5VDC so the HC is fine. Yes, pins should be tied... but none of that has anything to do with what I am asking.... Are there components I have not considered which would reduce the component count. For example, multiple opto couplers that are internally configured or have built in latches...finding a lower component, lower cost, smaller solution to my already working circuit was the reason I posted at all....