drDOC
Member level 3
Hi,
I am experienced in cmos design with 0.7 micron. The 1/f corner off course depends on a transistor and it's bias condition. But generally in this process the 1/f corner is 5 to 10kHz.
So my question: what would generally be the 1/f corner in 65nm processes or below.
My feeling is that 1/f will not improve because the smaller mos devices have thinner oxides and suffer from more surface effects. So I would expect that the 1/f corner should go to 100kHz even MHz ranges.
Can anybody comment on 1/f corners in different processes of similarly biased transistors?
I am experienced in cmos design with 0.7 micron. The 1/f corner off course depends on a transistor and it's bias condition. But generally in this process the 1/f corner is 5 to 10kHz.
So my question: what would generally be the 1/f corner in 65nm processes or below.
My feeling is that 1/f will not improve because the smaller mos devices have thinner oxides and suffer from more surface effects. So I would expect that the 1/f corner should go to 100kHz even MHz ranges.
Can anybody comment on 1/f corners in different processes of similarly biased transistors?