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how to simulate the offset of dynamic latched comparator?

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lhlbluesky

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how to simulate the offset of dynamic latched comparator?

the comp has one input,one threshold,two output(vout+ and vout-)
 

use ramp signal on one input, do trans simulation, and see when the vout changed from "0" to "1". Then you can see the offset between the inputs.
use Monte Carlo simulation, you can find the mismatch distribution
 

To calculate the resoltuion of dynamic comp, u one do the follwoing:
1) do the tran analysis,(Hspice) w.r.to clk , fix one i/p to trip threshold volatge of comp and change the other i/p..e.g
if vt=0.9 v, change vin from 0.899 to 0.901v, u will see at one point o/p will trip from 0 to 1, if not
change again vin from 0.901 to 0.9001...and so one.
resolution is change in vin that causes o/p to trip

regards
anil
 
You might find it easier to simulate as you would test; put
an integrator around the thing and close the loop to output
logic threshold. Then you just clock it until it settles.
 

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