Razavi's Sample and Hold ckt

in Razavi's Book P408 figure 12.4

He said, when hold clock rises, S1, S2 off, S3 on, Vout will be Vin*(C1/C2)

I did some simulation, set C1=C2=1pf, and found out Vout was 0 and VB=-0.3v (vin=0.6v)

what was wrong in my HSPICE code?



*Razavi P408 Fig 12.4

* Used to test ideal Sample and Hold circuits

.param vdd = 1

.subckt opamp 1 2 3 Aol=100K GBW=10Meg
G1 0 3 2 1 'Aol'
R3 3 0 1.
C3 3 0 'Aol/GBW/6.28318530717959'
.ends opamp


VSAMPLE clk_s 0 PWL(0 'vdd' 10n 'vdd' 10.001n 0 1 0)
VHOLD clk_h 0 PWL(0 0 10.0n 0 10.001n 'vdd' 1 'vdd')


Vin in 0 dc 0.6
gsw1 in a VCR PWL(1) clk_s 0 0,1e7 vdd,1m
gsw3 a 0 VCR PWL(1) clk_h 0 0,1e7 vdd,1m
c1 a b 1p
c2 b out 1p
gsw2 b out VCR PWL(1) clk_s 0 0,1e7 vdd,1m
xUamp b 0 out opamp Aol=100K GBW=10M

.print V(clk_s)
.print V(clk_h)
.print V(out)
.print V(b)
.print V(a)


.tran 5p 30n

.END

Added after 10 minutes:

Oh, found the answer,
the GBW was set too low
should be 100Meg