Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Clock multiply in VHDL

Status
Not open for further replies.
A

alexz

Full Member level 5
Joined
Nov 19, 2004
Messages
283
Helped
6
Reputation
12
Reaction score
3
Trophy points
1,298
Location
UK
Activity points
2,246
multiply in vhdl

How ( if possible at all) can I multiply a clock in VHDL?
Say, the input global clock is 25MHz, and I need to get around 80MHz internal to synchronize with another external bus.
 

vhdl multiply

What is your target FPGA? Depending on the answer you might be able to use a PLL or DCM to do the multiplication you need.
 

how to multiply clock

benradu said:
What is your target FPGA? Depending on the answer you might be able to use a PLL or DCM to do the multiplication you need.
Click to expand...

CPLD MAX 2 Altera
How can I use the PLL there?
 

multiply clock

I've seen somewhere a circuit that performs multiplication by 2 using a FF and a gate or so.
You get a short pulse every edge of your input signal. Is that helpful?
 

vhdl clock multiply

benradu said:
I've seen somewhere a circuit that performs multiplication by 2 using a FF and a gate or so.
You get a short pulse every edge of your input signal. Is that helpful?
Click to expand...

Well, not really :)
 

how to multiply a clock

why dont't to use oscillator or FPGA with PLL??? What is so special about MAX II?
 

maxii pll

Hey Guys!!

Don't MAX II CPLDs have DLLs or DCMs (Xilinx's) like structures which can be used to divide/multiply clock?

If not, I don't think anything can be done in FPGA/CPLD to generate 80Mhz clock from 25Mhz clock.

Regards.
 

fpga multiply clock

Iouri said:
why dont't to use oscillator or FPGA with PLL??? What is so special about MAX II?
Click to expand...

There is nothing special about MAX II.
I just don't need all the FPGA resources.
 

clock multiply

you cannot use HDL to do clk multiplication, as HDL is only able to do digital design...

however, if u have FPGA, then it might have the PLL feature tht can be used to do clk multiplication...

for altera FPGA... u need to use the megacore (IP) to use the PLL...

clk multiplication is considered analog stuff...

but... HDL can create clk divider...


regards
sp
 

max ii pll

Right. You can't use HDL do do clock multiplication (being a description language). But you can use HDL to describe a circuit that can do that. As I said, a multiplication by 2 can be done, the resulting signal looks more like pulses but is twice the input frequency.
See this link:
**broken link removed**
Trick # 4
Or search the Xilinx website for "Non-Synchronous Circuit Tricks"
 

fpga multiply clock by 2

to Alexz, FPGA and CPLD are very close to each other interms of price, you can probably get cyclone I device for the same price, yes you will need additional software to boot up FPGA, but on positive side you will have more flixability of manipulating the clocks, also keep in mind if you need to do the upgrade on the field, it would be much easy to update FPGA instead of CPLD


regards,
 

pll for clock multiplication fpga

Iouri said:
to Alexz, FPGA and CPLD are very close to each other interms of price, you can probably get cyclone I device for the same price, yes you will need additional software to boot up FPGA, but on positive side you will have more flixability of manipulating the clocks, also keep in mind if you need to do the upgrade on the field, it would be much easy to update FPGA instead of CPLD


regards,
Click to expand...

what about boot then?
CPLD has got some non volatile memory on chip
 

maxii clock divide

correct you need to boot them. you can generate *.rbf file and load it through SPI of the micro controller (I am assuming you have micro in your design)

But sometimes people using CPLD to store reset configuration word for the micro in CPLD, in this case use simple parallel latch with /OE to configure CPU, and than boot up FPGA

regards,
 

clock multiplication vhdl

You can use a Lattice MachXO part.

The MachXO is a small FPGA like the Altera MaxII, only the 2 larger size XO's (1200 and 2280 lut's) have 1 or 2 pll's (respectively). The XO's also have memory (distributed and Block) which the Altera folks don't. Price is the same.

Non-volatile
Single Chip solution (Flash on chip, boots into SRAM ~1ms)

Here's a link to their website


https://www.latticesemi.com/product...ource=topnav&jsessionid=ba306d3c28300x$B7$F8$[/url]
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top