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how to design a larger N PLL synthesizer.

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chmhero

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design a intege N synthesizer.

reference clock 50K
bandwidth 5KHz(big cap in chip).
N =1000 above

i set the Icp to 5uA, sb tell me the leakage current is so much, and the leakage curren will generate the spur , how to estimate the spur? how to design the PLL with less spur.

any advice is welcome .
 

who can help me ? thanks .
 

the nonideal effects in charge pump produce the spurs, usually harmonious of the compare frequency.the effective means to reduce the spurs is to eliminate or alleviate the nonidealities.
chmhero said:
design a intege N synthesizer.

reference clock 50K
bandwidth 5KHz(big cap in chip).
N =1000 above

i set the Icp to 5uA, sb tell me the leakage current is so much, and the leakage curren will generate the spur , how to estimate the spur? how to design the PLL with less spur.

any advice is welcome .
Click to expand...
 

You'd better adjust bandwidth to filter the spur. Perfect charge pump doesn't exists!
 

N=1000 is very large for CPPLL, and the bandwidth is so small that the VCO's noise contribution is too large. CPPLL is not a good solution for such a synthesizer. DDS may be more useful.
 

sorry ,the PLL is a clock multiplier. like the ADI 9883 or ICS1523.
both two chip have external component(cap and res). i am looking for a idea to t to avoid the external component .
 

chmhero:

I am sorry to say it is impossible to avoiding the external component.

Selina
 

Hi Chmhero,
In the e-book "CMOS PLL Synthesizers: Analysis and Design" chapter 5, you can find the solution for large N PLL.
 

You can reduce kvco based on good structure,then you can increase Icp and reduce spur.
 

paladinzlp said:
You can reduce kvco based on good structure,then you can increase Icp and reduce spur.
Click to expand...
yes, it's a good idea
i'm working on the same project recently, use a 30K fref to generate 20M output signal for local osc.
 

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