vhdl code for d flipflop

plz tell me vhdl code for d flipflop using structural modelling..


thanks

The Code:


library IEEE;
use IEEE.std_logic_1164.all;

entity d_ff_srss is
port (
d,clk,reset,set : in STD_LOGIC;
q : out STD_LOGIC);
end d_ff_srss;

architecture d_ff_srss of d_ff_srss is
begin
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
q <= '0';
elsif set='1' then
q <= '1';
else
q <= d;
end if;
end if;
end process;
end d_ff_srss;



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Originally Posted by divyak

plz tell me vhdl code for d flipflop using structural modelling..


thanks

Do you mean to describe D-trigger as a structure of not-and gates?

Just a supplement: rancohen_2000's code descibes a DFF with sync set/reset. Some DFFs like 7474 have async set/reset.

for asynch it will be:

library IEEE;
use IEEE.std_logic_1164.all;

entity d_ff_aras is
port (
d,clk,reset,set : in STD_LOGIC;
q : out STD_LOGIC);
end d_ff_aras;

architecture d_ff_aras of d_ff_aras is
begin
process(clk,reset,set)
begin
if reset='1' then
q <= '0';
elsif set='1' then
q <= '1';
elsif clk'event and clk='1' then
q <= d;
end if;
end process;
end d_ff_aras;

Hi divyak
I think you did not ask for DFF VHDL code in behavioral Modelling. You specifically asked for structural modelling.

for that you can write code for NAND gate and use it as a component in your design.
you can portmap the NAND gates as per your FF logic circuit. If it does help you it is ok, if you find some problem please let me know. I know you may face some problem in clocking the flip flop.

Here is what you are looking for ...

Code:

library ieee;
use ieee.std_logic_1164.all;

entity my_nand is
  
  port (
    a : in  std_logic;
    b : in  std_logic;
    c : in  std_logic;
    y : out std_logic);

end my_nand;

architecture behave of my_nand is

begin  -- behave

  y <= not (a and b and c);

end behave;
  

library ieee;
use ieee.std_logic_1164.all;
use work.all;

entity d_ff is
  
  port (
    clk   : in  std_logic;
    rst_n : in  std_logic;
    set_n : in  std_logic;
    d     : in  std_logic;
    q     : out std_logic;
    q_n   : out std_logic);

end d_ff;

architecture struct of d_ff is
component my_nand
  port (
    a : in  std_logic;
    b : in  std_logic;
    c : in  std_logic;
    y : out std_logic);
end component;
signal y0, y1, y2, y3: std_logic;
signal y4 : std_logic; -- := '0';
signal y5 : std_logic; -- := '1';
begin  -- struct
  q <= y4;
  q_n <= y5;
  
  my_nand0 : my_nand port map (set_n, y1,    y3,  y0 );
  my_nand1 : my_nand port map (clk,   rst_n, y0,  y1 );
  my_nand2 : my_nand port map (clk,   y3,    y1,  y2 );
  my_nand3 : my_nand port map (d,     rst_n, y2,  y3 );
  my_nand4 : my_nand port map (set_n, y1,    y5,  y4 );
  my_nand5 : my_nand port map (rst_n, y2,    y4,  y5 );
end struct;

Search online for your question.

Hi,
This is code wht u r asking....

entity Ngate is
port(a,b :in bit;
c :out bit);
end Ngate;

architecture behave of Ngate is
begin
process(a,b)
begin
c <= a nand b;
end process;
end behave;

entity not1 is
port( i :in bit;
j :out bit);
end not1;
architecture behave of not1 is
begin
j <= not i;
end behave;


entity Dflop is
port( D,clk :in bit;
Q :out bit;
Qb :out bit);
end Dlatch;

architecture struct of Dflop is

signal Db,c1,c2,cr1,cr2 : bit;
label U1,U2,U3,U4,U5;
component Ngate
port (a, b :in bit;
c :out bit);
end component;

component not1
port (i : in bit;
j : out bit);
end component;
for U1,U2,U3,U4 :Ngate
use entity Ngate(behave);
for U5 :not1
use entity not1(behave);
begin
process(cr1, cr2)
begin
Q <= cr1;
Qb <=cr2;
end process;
U1 : Ngate
port map(D,clk,c1);
U2 : Ngate
port map(clk,Db,c2);
U3 : Ngate
port map(c1,cr2,cr1);
U4 : Ngate
port map(c2,cr1,cr2);
U5 : not1
port map(D,Db);
end struct;

The Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dtri IS
PORT(
clk,clrn,prn : IN STD_LOGIC;
d : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END dtri;
ARCHITECTURE a OF dtri IS
BEGIN
PROCESS(clk,clrn,prn)
BEGIN
IF clrn='0' and prn/='0' THEN q<='0';
ELSIF prn='0' and clrn/='0' THEN q<='1';
ELSIF clrn='0' and prn='0' THEN q<='X';
ELSIF clk'event and clk='1' THEN q<=d;
END IF;
END PROCESS ;
END a;

error : Asynchronous Control "(null)" for DFF is initializing the DFF to a value other than logic "0" or logic "1"
help me , please ! thank so much !!!

3 remarks

1. This post is 5 years old
2. why are you trying to re-invent the wheel, the code above (#7) is correct
3. you're mixing behaviour and RTL