---
+ Post New Thread
Results 1 to 11 of 11
  1. #1
    Newbie level 4
    Points: 1,153, Level: 7
    divyak's Avatar
    Join Date
    Sep 2006
    Posts
    6
    Helped
    0 / 0
    Points
    1,153
    Level
    7

    vhdl program for d flip flop

    plz tell me vhdl code for d flipflop using structural modelling..


    thanks

    •   Alt25th October 2006, 13:09

      advertising

        
       

  2. #2
    Full Member level 2
    Points: 2,907, Level: 12
    Achievements:
    7 years registered

    Join Date
    Aug 2006
    Posts
    121
    Helped
    26 / 26
    Points
    2,907
    Level
    12

    vhdl code for d flip flop

    The Code:


    library IEEE;
    use IEEE.std_logic_1164.all;

    entity d_ff_srss is
    port (
    d,clk,reset,set : in STD_LOGIC;
    q : out STD_LOGIC);
    end d_ff_srss;

    architecture d_ff_srss of d_ff_srss is
    begin
    process(clk)
    begin
    if clk'event and clk='1' then
    if reset='1' then
    q <= '0';
    elsif set='1' then
    q <= '1';
    else
    q <= d;
    end if;
    end if;
    end process;
    end d_ff_srss;



    please press the "Helped"



  3. #3
    Full Member level 3
    Points: 2,313, Level: 11

    Join Date
    Jun 2005
    Posts
    151
    Helped
    15 / 15
    Points
    2,313
    Level
    11

    d flip flop vhdl code

    Quote Originally Posted by divyak
    plz tell me vhdl code for d flipflop using structural modelling..


    thanks
    Do you mean to describe D-trigger as a structure of not-and gates?



  4. #4
    Newbie level 5
    Points: 1,381, Level: 8

    Join Date
    Aug 2005
    Posts
    9
    Helped
    1 / 1
    Points
    1,381
    Level
    8

    vhdl code for d flipflop

    Just a supplement: rancohen_2000's code descibes a DFF with sync set/reset. Some DFFs like 7474 have async set/reset.



    •   Alt27th October 2006, 02:08

      advertising

        
       

  5. #5
    Full Member level 2
    Points: 2,907, Level: 12
    Achievements:
    7 years registered

    Join Date
    Aug 2006
    Posts
    121
    Helped
    26 / 26
    Points
    2,907
    Level
    12

    vhdl program for sr flip flop

    for asynch it will be:

    library IEEE;
    use IEEE.std_logic_1164.all;

    entity d_ff_aras is
    port (
    d,clk,reset,set : in STD_LOGIC;
    q : out STD_LOGIC);
    end d_ff_aras;

    architecture d_ff_aras of d_ff_aras is
    begin
    process(clk,reset,set)
    begin
    if reset='1' then
    q <= '0';
    elsif set='1' then
    q <= '1';
    elsif clk'event and clk='1' then
    q <= d;
    end if;
    end process;
    end d_ff_aras;





    •   Alt27th October 2006, 05:37

      advertising

        
       

  6. #6
    Full Member level 2
    Points: 2,125, Level: 10

    Join Date
    Oct 2006
    Location
    USA
    Posts
    138
    Helped
    19 / 19
    Points
    2,125
    Level
    10

    verilog code for d flip flop

    Hi divyak
    I think you did not ask for DFF VHDL code in behavioral Modelling. You specifically asked for structural modelling.

    for that you can write code for NAND gate and use it as a component in your design.
    you can portmap the NAND gates as per your FF logic circuit. If it does help you it is ok, if you find some problem please let me know. I know you may face some problem in clocking the flip flop.



  7. #7
    Advanced Member level 3
    Points: 9,200, Level: 22

    Join Date
    Jul 2004
    Posts
    891
    Helped
    168 / 168
    Points
    9,200
    Level
    22

    vhdl code for d flip-flop

    Here is what you are looking for ...
    Code:
    library ieee;
    use ieee.std_logic_1164.all;
    
    entity my_nand is
      
      port (
        a : in  std_logic;
        b : in  std_logic;
        c : in  std_logic;
        y : out std_logic);
    
    end my_nand;
    
    architecture behave of my_nand is
    
    begin  -- behave
    
      y <= not (a and b and c);
    
    end behave;
      
    
    library ieee;
    use ieee.std_logic_1164.all;
    use work.all;
    
    entity d_ff is
      
      port (
        clk   : in  std_logic;
        rst_n : in  std_logic;
        set_n : in  std_logic;
        d     : in  std_logic;
        q     : out std_logic;
        q_n   : out std_logic);
    
    end d_ff;
    
    architecture struct of d_ff is
    component my_nand
      port (
        a : in  std_logic;
        b : in  std_logic;
        c : in  std_logic;
        y : out std_logic);
    end component;
    signal y0, y1, y2, y3: std_logic;
    signal y4 : std_logic; -- := '0';
    signal y5 : std_logic; -- := '1';
    begin  -- struct
      q <= y4;
      q_n <= y5;
      
      my_nand0 : my_nand port map (set_n, y1,    y3,  y0 );
      my_nand1 : my_nand port map (clk,   rst_n, y0,  y1 );
      my_nand2 : my_nand port map (clk,   y3,    y1,  y2 );
      my_nand3 : my_nand port map (d,     rst_n, y2,  y3 );
      my_nand4 : my_nand port map (set_n, y1,    y5,  y4 );
      my_nand5 : my_nand port map (rst_n, y2,    y4,  y5 );
    end struct;



  8. #8
    Full Member level 1
    Points: 1,679, Level: 9

    Join Date
    Aug 2006
    Posts
    95
    Helped
    5 / 5
    Points
    1,679
    Level
    9

    d flipflop vhdl

    Search online for your question.



  9. #9
    Junior Member level 1
    Points: 1,204, Level: 7

    Join Date
    Sep 2006
    Location
    Mumbai
    Posts
    17
    Helped
    0 / 0
    Points
    1,204
    Level
    7

    d flip flop code in vhdl

    Hi,
    This is code wht u r asking....

    entity Ngate is
    port(a,b :in bit;
    c :out bit);
    end Ngate;

    architecture behave of Ngate is
    begin
    process(a,b)
    begin
    c <= a nand b;
    end process;
    end behave;

    entity not1 is
    port( i :in bit;
    j :out bit);
    end not1;
    architecture behave of not1 is
    begin
    j <= not i;
    end behave;


    entity Dflop is
    port( D,clk :in bit;
    Q :out bit;
    Qb :out bit);
    end Dlatch;

    architecture struct of Dflop is

    signal Db,c1,c2,cr1,cr2 : bit;
    label U1,U2,U3,U4,U5;
    component Ngate
    port (a, b :in bit;
    c :out bit);
    end component;

    component not1
    port (i : in bit;
    j : out bit);
    end component;
    for U1,U2,U3,U4 :Ngate
    use entity Ngate(behave);
    for U5 :not1
    use entity not1(behave);
    begin
    process(cr1, cr2)
    begin
    Q <= cr1;
    Qb <=cr2;
    end process;
    U1 : Ngate
    port map(D,clk,c1);
    U2 : Ngate
    port map(clk,Db,c2);
    U3 : Ngate
    port map(c1,cr2,cr1);
    U4 : Ngate
    port map(c2,cr1,cr2);
    U5 : not1
    port map(D,Db);
    end struct;



  10. #10
    Newbie level 1
    Points: 300, Level: 3
    Ikeuchi's Avatar
    Join Date
    Jul 2011
    Posts
    1
    Helped
    0 / 0
    Points
    300
    Level
    3

    Re: d flip flop code in vhdl

    The Code:
    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    ENTITY dtri IS
    PORT(
    clk,clrn,prn : IN STD_LOGIC;
    d : IN STD_LOGIC;
    q : OUT STD_LOGIC
    );
    END dtri;
    ARCHITECTURE a OF dtri IS
    BEGIN
    PROCESS(clk,clrn,prn)
    BEGIN
    IF clrn='0' and prn/='0' THEN q<='0';
    ELSIF prn='0' and clrn/='0' THEN q<='1';
    ELSIF clrn='0' and prn='0' THEN q<='X';
    ELSIF clk'event and clk='1' THEN q<=d;
    END IF;
    END PROCESS ;
    END a;

    error : Asynchronous Control "(null)" for DFF is initializing the DFF to a value other than logic "0" or logic "1"
    help me , please ! thank so much !!!



  11. #11
    Advanced Member level 1
    Points: 4,251, Level: 15

    Join Date
    Oct 2003
    Location
    Belgium
    Posts
    499
    Helped
    68 / 68
    Points
    4,251
    Level
    15

    Re: d flip flop code in vhdl

    3 remarks

    1. This post is 5 years old
    2. why are you trying to re-invent the wheel, the code above (#7) is correct
    3. you're mixing behaviour and RTL



+ Post New Thread
Please login