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cmos capacitor wth floating terminal

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mathi

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Hi all,

I want to create a capcitor that will hold a negative voltage. The top plate should have a connection to a source while the bottom plate is left floating. So basically i want to some how get electrons onto the bottom plate using the eletric field of the source. Is this possible in cmos process 35? If so how can i achieve this?
 

Hi,

Can you tell me what kind of circuit that needs this floating terminal capacitor???

Regards,
Shohdy
 

The capacitor will be used with a nmos transistor so that the second plate will be the gate of the transistor and it will be floating. The top plate of capacitor will be the new control gate of this transistor. This allows us to store charge which shifts the threshold voltage which can be then used to indentify between logic 1 and logic 0. I have attached a picture of the circuit.
 

Please refer to memories in Rabaey or Weste.

Regards
 

in single power supply design , negative volt is difficult
, I think you can shift negative -> positive voltage

float gate only use in flash memory design , general cmos no this layer .. and new CMOS process only use
M-i-M cap no use double poly for Cap
 

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