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verification question please

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salma ali bakr

salma ali bakr

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i read in a book about RTL verification this sentence:

"we define verifiable RTL as a combination of coding style and methodology techniques that, when used properly, will ensure cooperation and support for multiple EDA tools used during the course of verification"

well, i've just started to read about verification....so i can't really understand the relation of verification techniques with EDA tools used....what i understood about verification is that it is "to know that u r doing ur product right"....to be sure that ur RTL meets ur specs to decrease testing later....isn't that right

clear me up on that issue plz guys

thanks alot,
Salma:D
 

i'm not sure what the question is about. is it about verification or is it about RTL as in the quoted text ?

if i'm not mistaken, some of the synthesis tools will behave differently. for example, DC has some statements like full case on and all, which i believe could not be used for some other tool.

according to the excerpt, verifiable RTL is nothing but RTL, which can be used across tools. i.e. it does not use any design constructs, which might satisfy criteria for one particular tool alone.

hope i have been clear.
 

It could mean writing code in such a way which makes verification easier using EDA tools.
Maybe verification guys can offer more explanation.
 

salma ali bakr said:
i read in a book about RTL verification this sentence:

"we define verifiable RTL as a combination of coding style and methodology techniques that, when used properly, will ensure cooperation and support for multiple EDA tools used during the course of verification"

well, i've just started to read about verification....so i can't really understand the relation of verification techniques with EDA tools used....what i understood about verification is that it is "to know that u r doing ur product right"....to be sure that ur RTL meets ur specs to decrease testing later....isn't that right

clear me up on that issue plz guys

thanks alot,
Salma:D
Click to expand...
Hi,
Without reading that specific book/section I can only share my experience on this.

1. Writing RTL is at times done in a hurry that it contains race conditions. This would make it hard to verify easily across EDA tools as by definition race conditions can yiled different results in different tools.
2. Adding assertions inlined in RTL "help" in Verification as demonstrated by multiple teams, books etc.


HTH,
Ajeetha, CVC
www.noveldv.com
New Book: A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
https://www.systemverilog.us/
 
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