snowlandeg
Newbie level 3
salam ,,,
this is a VHDL code for generating a 10 sec pulse in for every minute
Entity T2 is
port ( clk : in std_logic ;
T : out std_logic );
end entity ;
architecture behv2 of T2 is
begin
process ( Clk )
variable PCount : Integer :=0 ;
variable SecCount : Integer := 0 ;
variable PC : Integer :=0 ;
variable SecC : Integer := 0 ;
begin
L1 : for PC in 0 to 24999999 loop
if (clk'event and clk = '1') then
PCount := PCount + 1 ;
if PCount = 24999999 then
SecCount := SecCount + 1 ;
end if ;
end if ;
end loop L1 ;
L2 : for SecC in 0 to 59 loop
if SecCount > 0 and SecCount < 10 then
T <= '1' ;
else T <= '0' ;
end if ;
end loop L2 ;
end process ;
end behv2 ;
the problem is when I start simulation in modelsim it goes so slowwwwwww
could any body help me fixing this problem
thanks in advance ,,,,
note " we need synthesible code "
this is a VHDL code for generating a 10 sec pulse in for every minute
Entity T2 is
port ( clk : in std_logic ;
T : out std_logic );
end entity ;
architecture behv2 of T2 is
begin
process ( Clk )
variable PCount : Integer :=0 ;
variable SecCount : Integer := 0 ;
variable PC : Integer :=0 ;
variable SecC : Integer := 0 ;
begin
L1 : for PC in 0 to 24999999 loop
if (clk'event and clk = '1') then
PCount := PCount + 1 ;
if PCount = 24999999 then
SecCount := SecCount + 1 ;
end if ;
end if ;
end loop L1 ;
L2 : for SecC in 0 to 59 loop
if SecCount > 0 and SecCount < 10 then
T <= '1' ;
else T <= '0' ;
end if ;
end loop L2 ;
end process ;
end behv2 ;
the problem is when I start simulation in modelsim it goes so slowwwwwww
could any body help me fixing this problem
thanks in advance ,,,,
note " we need synthesible code "