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Need help with bus interfacing

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david119

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Hi everyone,

Let me start by saying that I'm new to CPLDs and that I'm working with the Lattice ispLEVER starter software. I started my project with their 5000MX chip in mind.

In my design I want to connect several design blocks (memory, LCD, ALU, ect) together with a bus. I thought I could use tri-state devices to prevent bus contention, but I can't find any in the symbol library to implement this. Also I can't put "Z" into the VHDL without error.

I was told that MUXs could be used instead of tri-state devices. How is this so? I understand how you could use a MUX to run the addressing of the blocks. But how can you use a MUX to effectively "isolate" and "not isolate" a block from the bus?

Thanks in advance

david119
 

I think you can implement tri state only in the external pins of the device not internal.

Regards
 

yes you can implimented tri-state buses on VHDL code, but actual immplimentatin in FPGA/CPLD will replace with some wierd logic.
Due to the fact there is no resources inside CPLD/FPGA to have actual tristate bus use mux and decoders. input of each device feeeding throught mux. And ALL devices inside CPLD using sepate transmit and recieve buses, no bi directional busses also!


Regards,
 

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