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LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY shift_reg IS
GENERIC(number_of_bits : integer;
);
PORT( reset : in std_logic;
init_value : in std_logic_vector(number_of_bits-1 downto 0); -- outside of this block
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
END shift_reg;
architecture behave of shift_reg is
begin
process(clk)
variable reg: std_logic_vector(number_of_bits-1 downto 0);
variable i: integer;
begin
if reset = '1' then
reg := init_value;
elsif rising_edge(clk) then
for i in number_of_bits-1 downto 1 loop
reg(i):=reg(i-1);
end loop;
reg(0):=data_in;
end if;
data_out <= reg(number_of_bits-1);
end process;
end behave;
it is possible that this code has some synthax mistakes. Sorry, but I have wrote it without having any tool.
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