Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Digital demodulation using FPGA for QPSK signal

Status
Not open for further replies.
S

shaomiss

Junior Member level 1
Joined
Dec 25, 2002
Messages
17
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
45
Hi,i want to use FPGA to demodulate QPSK signal.
IF =140MHz
BW=3.5MHz
i want to use 70MHz Clock sample the IF signal,dose it work?
 

Digital Demodulation

it's better if u can use a DDC at the front end b4 demodulation to convert this IF to baseband or very near to the baseband. B/w of 3.5Mhz is not a problem for an FPGA to perform a QPSK demodulation.
what is the data rate required?
 

Digital Demodulation

70Mhz will not work, 60Mhz-65Mhz maybe good.

if you use 70Mhz sampling clock, the sampled signal's negative spectrum will be alias with positive spectrum, and you will not demodulate your PSK signal.

if you use 60M-65Mhz sampling clock, the sampled digital signal's main spectrum will be located in 10M-20MHz, and the alias effect will not occur.
 

Re: Digital Demodulation

Hi

I want to ask a question about the subject. Can we implement such a demodulation with DSPs? Is there a DSP card for this application (TI or Motorola)? I want to learn whether such a demodulation can be implemented on a DSP using simulink automatic code generation tool.

Thanks
 

Digital Demodulation

Hi emrek,
u can use DSPs to implement digital demodulators provided the data rate is low.
For higher data rate systems the no:eek:f MAC computations will be morem, and u require many multipliers to work simultaneously to sustain the data rate. The difference in the no:eek:f Multipliers for the DSPs and FPGAs are high, and so FPGA can give a better performance for the same compared to DSPs
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top