faye_hongdou
Member level 1
I want to coding a digital QAM/QPSK demodulator. In input interface module, I should remove the DC offset that added to the input data. How can I realize this using HDL?
I saw a plan which can be summarized as follows.
The IF digital input data is 12 bits. The upper 10 bits is used, and lower 2bits are not used. The DC offset is symboled as dc_bias.
They accumulate N samples to a 24-bit register, then output its high 8 bits. And N=2^14=16384.
I understand that the dc_bias is the average of the signal, and is updated every N samples. But why output the high 8 bits, not the high 14 bits?
Anyone can explian this for me? Thanks a lot.
I saw a plan which can be summarized as follows.
The IF digital input data is 12 bits. The upper 10 bits is used, and lower 2bits are not used. The DC offset is symboled as dc_bias.
They accumulate N samples to a 24-bit register, then output its high 8 bits. And N=2^14=16384.
I understand that the dc_bias is the average of the signal, and is updated every N samples. But why output the high 8 bits, not the high 14 bits?
Anyone can explian this for me? Thanks a lot.
